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january 2000 1/190 rev. 3.0 st90158 - st90135 8/16-bit mcu family with up to 64k rom/otp/eprom and up to 2k ram n register file based 8/16 bit core architecture with run, wfi, slow and halt modes n 0 - 16 mhz operation @ 5v 10%, -40 cto +85 c and 0 c to +70 c operating temperature ranges n 0 - 14 mhz operation @ 3v 10% and 0 cto +70 c operating temperature range n fully programmable pll clock generator, with frequency multiplication and low frequency, low cost external crystal n minimum 8-bit instruction cycle time: 83ns - (@ 24 mhz internal clock frequency) n minimum 16-bit instruction cycle time: 250ns - (@ 24 mhz internal clock frequency) n internal memory: eprom/otp/rom 16/24/32/48/64k bytes romless version available ram 512/768/1k/1.5k/2k bytes n maximum external memory: 64k bytes n 224 general purpose registers available as ram, accumulators or index pointers (register file) n 80-pin plastic quad flat package and 80-pin thin quad flat package n 67 fully programmable i/o bits n 8 external and 1 non-maskable interrupts n dma controller and programmable interrupt handler n single master serial peripheral interface n two 16-bit timers with 8-bit prescaler, one usable as a watchdog timer (software and hardware) n three (st90158) or two (st90135) 16-bit multifunction timers, each with an 8 bit prescaler, 12 operating modes and dma capabilities n 8 channel 8-bit analog to digital converter, with automatic voltage monitoring capabilities and external reference inputs n two (st90158) or one (st90135) serial communication interfaces with asynchronous, synchronous and dma capabilities n rich instruction set with 14 addressing modes n division-by-zero trap generation n versatile development tools, including assembler, linker, c-compiler, archiver, source level debugger and hardware emulators with real-time operating system available from third parties device summary device program memory (bytes) ram (bytes) mft sci package st90135 16k rom 512 2 1 pqfp80 24k rom 768 2 1 32k rom 1k 2 1 st90158 48k rom 1.5k 3 2 64k rom 2k 3 2 pqfp80/ tqfp80 st90e158 64k eprom 2k 3 2 cqfp80 st90e158lv 64k eprom 2k 3 2 cqfp80 st90t158 64k otp 2k 3 2 pqfp80 st90t158lv 64k otp 2k 3 2 pqfp80/ tqfp80/ st90r158 romless 2k 3 2 pqfp80/ tqfp80 pqfp80 tqfp80 9
2/190 table of contents 190 9 1 general description . . . . . . ................................................ 6 1.1 introduction . . . . . . . . . . . . . ............................................ 6 1.1.1 st9+ core . . . ..................................................... 6 1.1.2 power saving modes . . . . . . . . . . . . . ................................... 6 1.1.3 system clock . . . . . . . . . . . . . ......................................... 6 1.1.4 i/o ports . . . . . . . . . . . . . . ............................................ 6 1.1.5 multifunction timers (mft) . . . ......................................... 7 1.1.6 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 watchdog timer (wdt) . . . . . . . . . ................................ ..... 7 1.1.8 serial peripheral interface (spi) . . . . . ................................... 7 1.1.9 serial communications controllers (sci) . . . . . . . . . . . . ..................... 7 1.1.10 analog/digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............ 7 1.2 pin description . . .................................................... 10 1.3 i/o port pins . . . . . . . . . . . . . . . . . ........................................ 13 2 device architecture . . . . . . . . . . ........................................... 18 2.1 core architecture . . . . . . . . . . . . . . . . . . ................................ 18 2.2 memory spaces . . . . . . . . . . . . . . ........................................ 18 2.2.1 register file . . . . . . . . . . . . . . . . . . . . . . . . .............................. 18 2.2.2 register addressing . . . . . ........................................... 20 2.3 system registers . . . . . . . . . . . . . . . . . . . . . . .............................. 21 2.3.1 central interrupt control register . . . . . . . . . . . ........................... 21 2.3.2 flag register . . . . . . ............................................... 22 2.3.3 register pointing techniques . ........................................ 23 2.3.4 paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.5 mode register . . . . . ............................................... 26 2.3.6 stack pointers . . . . . . . . . . . . . . . . . . . . . ................................ 27 2.4 memory organization . . . . . . . . . . . . . . . ................................. 29 2.5 memory management unit . . . . . . . . . . .................................. 30 2.6 address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.1 addressing 16-kbyte pages . . . . . . . . . ............................. .... 31 2.6.2 addressing 64-kbyte segments . . . . . .................................. 32 2.7 mmu registers . ...................................................... 32 2.7.1 dpr[3:0]: data page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... 32 2.7.2 csr: code segment register ........................................ 34 2.7.3 isr: interrupt segment register . . . . . . . . . .............................. 34 2.7.4 dmasr: dma segment register . . . . . . . . .............................. 34 2.8 mmu usage . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 36 2.8.1 normal program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 36 2.8.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 36 2.8.3 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 36 3 register and memory map ............................. ................... 37 3.1 memory configuration . . . . . . . . . . . . . ............................. .... 37 3.2 eprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 memory map . . . . . . . . . . ........................................... .... 39 3.4 st90158/135 register map . . . . . . . . . . . .................................. 40 4 interrupts . . ......................... .................................... 48 4.1 introduction . . . . . . . . . . . . . ........................................... 48 4.2 interrupt vectoring ................................................ 48
3/190 table of contents 9 4.2.1 divide by zero trap . . . . . . . . . . . . . . . . ................................. 48 4.2.2 segment paging during interrupt routines . ......................... .... 49 4.3 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 priority level arbitration . . . ........................................ 49 4.4.1 priority level 7 (lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.2 maximum depth of nesting . . . ........................................ 49 4.4.3 simultaneous interrupts . . . . . . . . . . . . ................................. 49 4.4.4 dynamic priority level modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5 arbitration modes . . . . . . . . . . . . . . . . . .................................. 50 4.5.1 concurrent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5.2 nested mode . . . . . . ............................................... 53 4.6 external interrupts . . . . . . . . . . . . . . . . . . .............................. 55 4.7 top level interrupt . . . . . . . . . . . . . . . . . ................................ 57 4.8 on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... 57 4.9 interrupt response time . ........................................... 58 4.10 interrupt registers . . ........................................... .... 59 5 on-chip direct memory access (dma) . . . . .................................. 63 5.1 introduction . . . . . . . . . . . . . ........................................... 63 5.2 dma priority levels . . . ........................................... .... 63 5.3 dma transactions . . . . . . . . . . . ........................................ 64 5.4 dma cycle time . . . . . . . . . . . . . . . ........................................ 66 5.5 swap mode . . . . . . . . . . . . ........................................... .... 66 5.6 dma registers . . . . . . . . . . . . ........................................... 67 6 reset and clock control unit (rccu) . . . ............................. .... 68 6.1 introduction . . . . . . . . . . . . . ........................................... 68 6.2 clock control unit . . . . . . . ........................................... 68 6.2.1 clock control unit overview . . ........................................ 68 6.3 clock management . . . . . . . . . . ........................................ 69 6.3.1 pll clock multiplier programming . . . . ............................. .... 70 6.3.2 cpu clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.3 peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 71 6.3.5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 71 6.4 clock control registers . . . . . . . . . . . . . . .............................. 74 6.5 oscillator characteristics . . . . . . . . . . . .............................. 77 6.6 reset/stop manager . . . . . . ........................................... 79 6.6.1 reset pin timing . . . . . . . . . . . . . . . . ................................. 80 6.7 external stop mode . . ........................................... .... 80 7 external memory interface (extmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.1 introduction . . . . . . . . . . . . . ........................................... 81 7.2 external memory signals . . . . . . . . . . . . . . . . . ........................... 82 7.2.1 as: address strobe . . . . . . . . . . . . . . . . . . . . . ........................... 82 7.2.2 ds: data strobe . . . . ........................................... .... 82 7.2.3 ds2: data strobe 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2.4 rw: read/write . . . . ............................................... 85 7.2.5 breq, back: bus request, bus acknowledge . . . . . . . . . . . . . . . . . . . ........ 85 7.2.6 port 0 . . . . . . .................................................... 86
4/190 table of contents 1 7.2.7 port 1 . . . . . . .................................................... 86 7.2.8 wait: external memory wait . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 86 7.3 register description . ............................................... 87 8 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................ 90 8.1 introduction . . . . . . . . . . . . . ........................................... 90 8.2 specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 90 8.3 port control registers . . . . . . . . . . . . . . . . . . ........................... 90 8.4 input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.5 alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . ........... 95 8.5.1 pin declared as i/o . . ............................................... 95 8.5.2 pin declared as an alternate input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.5.3 pin declared as an alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6 i/o status after wfi, halt and reset . . . . . . . . . . . . . . . . . . . . . . ........... 95 9 on-chip peripherals . . . . . . . . . . . ........................................... 96 9.1 timer/watchdog (wdt) . . . . . . . . . . . . . .................................. 96 9.1.1 introduction . . . . . . . . . . . . ........................................... 96 9.1.2 functional description . . . . . . ........................................ 97 9.1.3 watchdog timer operation . . . . . . . ................................ .... 98 9.1.4 wdt interrupts ................................................... 100 9.1.5 register description . . . . . .......................................... 101 9.2 multifunction timer (mft) . . . . . . . . . . . . . . . . . . . . . . . . ................... 103 9.2.1 introduction . . . . . . . . . . . . .......................................... 103 9.2.2 functional description . . . . . . ....................................... 105 9.2.3 input pin assignment . . . . . . . . . . . . . ................................. 108 9.2.4 output pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.2.5 interrupt and dma . . . . . . . . . . . . . . . . ................................ 114 9.2.6 register description . . . . . .......................................... 116 9.3 standard timer (stim) . .............................................. 127 9.3.1 introduction . . . . . . . . . . . . .......................................... 127 9.3.2 functional description . . . . . . ....................................... 128 9.3.3 interrupt selection . . . .............................................. 129 9.3.4 register mapping . . . . . . . .......................................... 129 9.3.5 register description . . . . . .......................................... 130 9.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . .......... 131 9.4.1 introduction . . . . . . . . . . . . .......................................... 131 9.4.2 device-specific options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.4.3 functional description . . . . . . ....................................... 132 9.4.4 interrupt structure . . . .............................................. 133 9.4.5 working with other protocols . . . . ................................... 134 9.4.6 i2c-bus interface . . . .............................................. 134 9.4.7 s-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 137 9.4.8 im-bus interface . . . . . . . . . . . ....................................... 138 9.4.9 register description . . . . . .......................................... 139 9.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.5.1 introduction . . . . . . . . . . . . .......................................... 141 9.5.2 functional description . . . . . . ....................................... 142 9.5.3 sci operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.5.4 serial frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5/190 table of contents 1 9.5.5 clocks and serial transmission rates . ................................ 149 9.5.6 sci initialization procedure . . . . . . . . . . . . ............................. 149 9.5.7 input signals . . . . . . . . . . . . . . ....................................... 151 9.5.8 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 151 9.5.9 interrupts and dma . . . . . . . . . ....................................... 152 9.5.10 register description . .............................................. 155 9.6 eight-channel analog to digital converter (a/d) . . . . . . . . . . . . . . . . . . . 166 9.6.1 introduction . . . . . . . . . . . . .......................................... 166 9.6.2 functional description . . . . . . ....................................... 167 9.6.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 169 9.6.4 register description . . . . . .......................................... 170 10 electrical characteristics . . . . ........................................ 174 11 general information ................................................... 188 11.1 package mechanical data . . . . . . . . . . . . . . . . . .......................... 188 11.2 80-pin plastic quad flat package . . . . ................................ 188 11.3 ordering information . . . . . . . . . . . . . ................................. 189
6/190 st90158 - general description 1 general description 1.1 introduction the st90158 and st90135 microcontrollers are developed and manufactured by stmicroelectron- ics using a proprietary n-well cmos process. their performance derives from the use of a flexi- ble 256-register programming model for ultra-fast context switching and real-time event response. the intelligent on-chip peripherals offload the st9 core from i/o and data management processing tasks allowing critical application tasks to get the maximum use of core resources. the new-gener- ation st9 mcu devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 st9+ core the advanced core consists of the central processing unit (cpu), the register file, the inter- rupt and dma controller, and the memory man- agement unit. the mmu allows addressing of up to 4 megabytes of program and data mapped into a single linear space. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit inter- rupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture makes the st9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. 1.1.2 power saving modes to optimize performance versus power consump- tion, a range of operating modes can be dynami- cally selected. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). slow mode . power consumption can be signifi- cantly reduced by running the cpu and the periph- erals at reduced clock speed using the cpu pres- caler and ccu clock divider (pll not used) or by using the ck_af external clock. wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the ccu. in this mode, the power consumption of the device can be reduced by more than 95% (low power wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode. 1.1.3 system clock a programmable pll clock generator allows standard 3 to 5 mhz crystals to be used to obtain a large range of internal frequencies up to 24 mhz. 1.1.4 i/o ports the i/o lines are grouped into up to nine 8-bit i/o ports and can be configured on a bit basis to pro- vide timing, status signals, an address/data bus for interfacing to external memory, timer inputs and outputs, analog inputs, external interrupts and se- rial or parallel i/o. 9
7/190 st90158 - general description 1.1.5 multifunction timers (mft) each multifunction timer has a 16-bit up/down counter supported by two 16-bit compare regis- ters and two 16-bit input capture registers. timing resolution can be programmed using an 8-bit pres- caler. multibyte transfers between the peripheral and memory are supported by two dma channels. 1.1.6 standard timer (stim) the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes. 1.1.7 watchdog timer (wdt) the watchdog timer can be used to monitor sys- tem integrity. when enabled, it generates a reset after a timeout period unless the counter is re- freshed by the application software. for additional security, watchdog function can be enabled by hardware using a specific pin. 1.1.8 serial peripheral interface (spi) the spi bus is used to communicate with external devices via the spi, or i c bus communication standards. the spi uses one or two lines for serial data and a synchronous clock signal. 1.1.9 serial communications controllers (sci) each sci provides a synchronous or asynchro- nous serial i/o port using two dma channels. baud rates and data formats are programmable. 1.1.10 analog/digital converter (adc) the adcs provide up to 8 analog inputs with on- chip sample and hold. the analog watchdog gen- erates an interrupt when the input voltage moves out of a preset threshold. 9
8/190 st90158 - general description figure 1. st90158 block diagram 256 bytes register file ram up to 2 kbytes st9+ core 8/16 bits cpu interrupt management memory bus rccu register bus watchdog oscin oscout reset intclk ckaf as wait nmi r/w ds mft1 mft0 t0outa t0outb t0ina t0inb eprom/ rom/ot p up to 64 kbytes wdin wdout hw0sw1 all alternate functions ( italic characters ) are mapped on port2 through port9 int0-7 mft3 t3outa t3outb t3ina t3inb t1outa t1outb t1ina t1inb address data port0 sdi sdo sck p1[7:0] p0[7:0] spi i 2 c/im bus stim sci0 extrg ain[7:0] tx0ckin rx0ckin s0in dcd0 s0out clk0out rts0 stout addre ss port1 fully prog. i/os a/d converter with analog watchdog p0[7:0] p1[7:0] p2[6:0] p4[7:0] p5[7:3], p5.1 p6[6:0] p7[7:0] p8[7:0] p9[7:4], p9[2:0] sci1 tx1ckin rx1ckin s1in dcd1 s1out clk1out rts1 9
9/190 st90158 - general description figure 2. st90135 block diagram 256 bytes register file ram up to 1 kbyte st9+ core 8/16 bits cpu interrupt management memory bus rccu address data port0 register bus watchdog oscin oscout reset intclk ckaf as wait nmi r/w ds sdi sdo sck p1[7:0] p0[7:0] mft3 mft1 spi i 2 c/im bus t1outa t1outb t1ina t1inb stim sci0 rom up to 32 kbytes extrg ain[7:0] tx0ckin rx0ckin s0in dcd0 s0out clk0out rts0 stout all alternate functions ( italic characters ) are mapped on port2 through port9 int0-7 address port1 fully prog. i/os t3outa t3outb t3ina t3inb wdin wdout hw0sw1 a/d converter with analog watchdog p0[7:0] p1[7:0] p2[6:0] p4[7:0] p5[7:3], p5.1 p6[6:0] p7[7:0] p8[7:0] p9[7:4], p9[2:0] 9
10/190 st90158 - general description 9 1.2 pin description as : address strobe (output, active low, 3-state). address strobe is pulsed low once at the begin- ning of each memory cycle. the rising edge of as indicates that address, read/write (r/w), and data memory signals are valid for memory trans- fers. under program control, as can be placed in a high-impedance state along with port 0, port 1 and data strobe (ds). ds : data strobe (output, active low, 3-state). data strobe provides the timing for data movement to or from port 0 for each memory transfer. during a write cycle, data out is valid at the leading edge of ds. during a read cycle, data in must be valid pri- or to the trailing edge of ds. when the st90158 accesses on-chip memory, ds is held high during the whole memory cycle. it can be placed in a high impedance state along with port 0, port 1 and as. reset : reset (input, active low). the st9+ is ini- tialised by the reset signal. with the deactivation of reset, program execution begins from the memory location pointed to by the vector con- tained in memory locations 00h and 01h. r/w : read/write (output, 3-state). read/write de- termines the direction of data transfer for external memory transactions. r/w is low when writing to external memory, and high for all other transac- tions. it can be placed in high impedance state along with port 0, port 1, as and ds. oscin, oscout : oscillator (input and output). these pins connect a parallel-resonant crystal (3 to 5 mhz), or an external source to the on-chip clock oscillator and buffer. oscin is the input of the oscillator inverter and internal clock generator; oscout is the output of the oscillator inverter. hw0_sw1: when connected to v dd through a 1k pull-up resistor, the software watchdog option is selected. when connected to v ss through a 1k pull-down resistor, the hardware watchdog option is selected. v pp : programming voltage for eprom/otp de- vices. must be connected to v ss in user mode through a 10 kohm resistor. av dd : analog v dd of the analog to digital con- verter. av ss : analog v ss of the analog to digital con- verter. v dd : main power supply voltage (5v 10%). v ss : digital circuit ground. p0[7:0], p1[7:0]: ( input/output , ttl or cmos compatible ). 16 lines grouped into i/o ports provid- ing the external memory interface for addressing 64kbytes of external memory. p0[7:0], p1[7:0], p2[6:0], p4[7:0], p5[7:3], p5.1, p6[6:0], p7[7:0], p8[7:0], p9[7:4], p9[2:0]: i/o port lines (input/output, ttl or cmos compati- ble). i/o lines grouped into i/o ports of 8 bits, bit programmable under program control as general purpose i/o or as alternate functions.
11/190 st90158 - general description 1 pin description (cont'd) figure 3. 80-pin tqfp pin-out *eprom or otp devices only st90158/st90135 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 p6.6 p6.5/rw p6.4 p6.3 p6.2 p6.1 p6.0 p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 p1.3/a11 p1.2/a10 p1.1/a9 ad6/p0.6 v ss ad7/p0.7 v dd as ds v pp * p4.0 p4.1 intclk/p4.2 stout/p4.3 wdout/i nt0/p4.4 int4/p4.5 t0outb/int5 /p4.6 t0outa/p4.7 p2.0 p2.1 p2.2 p2.3 p2.4 1 20 21 40 41 60 61 80 p2.5 p2.6 s1out/p9.0 t0outb/s1in/p9.1 tx1ckin/clk1out/p9.2 s0out/rx1ckin/p9.4 s0in/p9.5 int2/sck/p9.6 int6/sdo/p9.7 ain0/rx0ckin/wdin/extrg/p7.0 ain1/t0inb/sdi/p7.1 ain2/clk0out/tx0ckin/p7.2 ain3/t0ina/p7.3 ain4/p7.4 ain5/p7.5 ain6/p7.6 ain7/p7.7 av dd av ss nmi/t3outb/p8.7 p1.0/a8 reset oscin v ss oscout p5.1/sdi hw0sw1 p5.3 p5.4/t1outa/dcd0 p5.5/t1out1/rts0 p5.6/t3outa/dcd1 p5.7/t3outb/rts1/ckaf v dd p8.0/t3ina p8.1/t1inb p8.2/int1/t1outa p8.3/int3/t1outb p8.4/t1ina/wa it/wdout p8.5/t3inb p8.6/int7/t3outa
12/190 st90158 - general description pin description (cont'd) figure 4. 80-pin pqfp pin-out ad4/p0.4 ad5/p0.5 ad6/p0.6 v ss ad7/p0.7 v dd as ds v pp * p4.0 p4.1 intclk/p4.2 stout/p4.3 int0/wdout/p4.4 int4/p4.5 int5/t0outb/p4.6 t0outa/p4.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 p6.6 p6.5/rw p6.4 p6.3 p6.2 p6.1 p6.0 p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 p1.3/a11 p1.2/a10 p1.1/a9 p1.0/a8 reset oscin v ss oscout p5.1/sdi hw0sw1 p5.3 p5.4/t1outa/dcd0 p5.5/t1outb/rts0 p5.6/t3outa/dcd1 p5.7/t3outb/rts1/ck_af v dd p8.0/t3ina p8.1/t1inb p8.2/t1outa/int1 p8.3/t1outb/int3 p8.4/t1ina/wait/wdout p8.5/t3inb p8.6/int7/t3outa p8.7/nmi/t3outb av ss s1out/p9.0 t0outb/s1in/p9.1 tx1ckin/clk1out/p9.2 s0out/rx1ckin/p9.4 s0in/p9.5 int2/sck/p9.6 int6/sdo/p9.7 ain0/rx0ckin/wdin/extrg/p7.0 ain1/t0inb/p7.1 ain2/clk0out/tx0ckin/p7.2 ain3/t0ina/p7.3 ain4/p7.4 ain5/p7.5 ain6/p7.6 ain7/p7.7 av dd 1 80 24 40 64 st90158/st90135 *eprom or otp devices only 9
13/190 st90158 - general description 1.3 i/o port pins all the ports of the device can be programmed as input/output or in input mode, compatible with ttl or cmos levels (except where schmitt trig- ger is present). each bit can be programmed indi- vidually (refer to the i/o ports chapter). ttl/cmos input for all those port bits where no input schmitt trig- ger is implemented, it is always possible to pro- gram the input level as ttl or cmos compatible by programming the relevant pxc2.n control bit. refer to the section titled ainput/output bit config- urationo in the i/o ports chapter . push-pull/od output the output buffer can be programmed as push- pull or open-drain: attention must be paid to the fact that the open-drain option corresponds only to a disabling of p-channel mos transistor of the buffer itself: it is still present and physically con- nected to the pin. consequently it is not possible to increase the output voltage on the pin over v dd +0.3 volt, to avoid direct junction biasing. table 1. i/o port characteristics legend: wpu = weak pull-up, od = open drain input output weak pull-up reset state port 0 ttl/cmos push-pull/od yes bidirectional wpu port 1 ttl/cmos push-pull/od yes bidirectional wpu port 2 ttl/cmos push-pull/od no bidirectional port 4 schmitt trigger push-pull/od yes bidirectional wpu port 5 schmitt trigger push-pull/od yes bidirectional wpu port 6 ttl/cmos push-pull/od no bidirectional port 7 schmitt trigger push-pull/od yes bidirectional wpu port 8 schmitt trigger push-pull/od yes bidirectional wpu port 9 schmitt trigger push-pull/od yes bidirectional wpu 9
14/190 st90158 - general description i/o port pins (cont'd) how to configure the i/o ports to configure the i/o ports, use the information in table 1, table 2 and the port bit configuration ta- ble in the i/o ports chapter (see page 92). input note = the hardware characteristics fixed for each port line in table 1. if input note = ttl/cmos, either ttl or cmos input level can be selected by software. if input note = schmitt trigger, selecting cmos or ttl input by software has no effect, the input will always be schmitt trigger. alternate functions (af) = more than one af cannot be assigned to an i/o pin at the same time: an alternate function can be selected as follows. af inputs: af is selected implicitly by enabling the corre- sponding peripheral. exception to this are a/d inputs which must be explicitly selected as af by software. af outputs or bidirectional lines: in the case of outputs or i/os, af is selected explicitly by software. example 1: sci data input af: s0in, port: p9.5, port style: input schmitt trigger. write the port configuration bits: p9c2.5=1 p9c1.5=0 p9c0.5=1 enable the sci peripheral by software as de- scribed in the sci chapter. example 2: sci data output af: s0out, port: p9.4 output push-pull (config- ured by software). write the port configuration bits: p9c2.4=0 p9c1.4=1 p9c0.4=1 example 3: adc data input af: ain0, port : p7.0, input note: does not apply to adc write the port configuration bits: p7c2.0=1 p7c1.0=1 p7c0.0=1 example 4: external memory i/o af: ad0, port : p0.0 write the port configuration bits: p0c2.0=0 p0c1.0=1 p0c0.0=1 table 2. i/o port description and alternate functions port name general purpose i/o pin no. alternate functions tqfp pqfp p0.0 all ports useable for general pur- pose i/o (input, output or bidirec- tional) 75 77 ad0 i/o address/data bit 0 mux p0.1 76 78 ad1 i/o address/data bit 1 mux p0.2 77 79 ad2 i/o address/data bit 2 mux p0.3 78 80 ad3 i/o address/data bit 3 mux p0.4 79 1 ad4 i/o address/data bit 4 mux p0.5 80 2 ad5 i/o address/data bit 5 mux p0.6 1 3 ad6 i/o address/data bit 6 mux p0.7 3 5 ad7 i/o address/data bit 7 mux p1.0 60 62 a8 i/o address bit 8 p1.1 61 63 a9 i/o address bit 9 p1.2 62 64 a10 i/o address bit 10 9
15/190 st90158 - general description p1.3 all ports useable for general pur- pose i/o (input, output or bidirec- tional) 63 65 a11 i/o address bit 11 p1.4 64 66 a12 i/o address bit 12 p1.5 65 67 a13 i/o address bit 13 p1.6 66 68 a14 i/o address bit 14 p1.7 67 69 a15 i/o address bit 15 p2.0 16 18 i/o p2.1 17 19 i/o p2.2 18 20 i/o p2.3 19 21 i/o p2.4 20 22 i/o p2.5 21 23 i/o p2.6 22 24 i/o p4.0 8 10 i/o p4.1 9 11 i/o p4.2 10 12 intclk o internal main clock p4.3 11 13 stout o standard timer output p4.4 12 14 int0 i external interrupt 0 wdout o watchdog timer output p4.5 13 15 int4 i external interrupt 4 p4.6 14 16 int5 i external interrupt 5 t0outb o mf timer 0 output b 1) p4.7 15 17 t0outa o mf timer 0 output a 1) p5.1 55 57 sdi i spi serial data in p5.3 53 55 i/o p5.4 52 54 t1outa o mf timer 1 output a dcd0 i sci0 data carrier detect p5.5 51 53 rts0 o sci0 request to send t1outb o mf timer 1 output b p5.6 50 52 t3outa o mf timer 3 output a dcd1 i sci1 data carrier detect 1) p5.7 49 51 rts1 o sci1 request to send 1) t3outb o mf timer 3 output b ck_af i external clock input p6.0 68 70 i/o port name general purpose i/o pin no. alternate functions tqfp pqfp 9
16/190 st90158 - general description p6.1 all ports useable for general pur- pose i/o (input, output or bidirec- tional) 69 71 i/o p6.2 70 72 i/o p6.3 71 73 i/o p6.4 72 74 i/o p6.5 73 75 r/w o read/write p6.6 74 76 i/o p7.0 30 32 ain0 i a/d analog input 0 rx0ckin i sci0 receive clock input wdin i t/wd input extrg i a/d external trigger p7.1 31 33 ain1 i a/d analog input 1 t0inb i mf timer 0 input b 1) sdi i spi serial data in p7.2 32 34 ain2 i a/d analog input 2 clk0out o sci0 byte sync clock output tx0ckin i sci0 transmit clock input p7.3 33 35 ain3 i a/d analog input 3 t0ina i mf timer 0 input a 1) p7.4 34 36 ain4 i a/d analog input 4 p7.5 35 37 ain5 i a/d analog input 5 p7.6 36 38 ain6 i a/d analog input 6 p7.7 37 39 ain7 i a/d analog input 7 p8.0 47 49 t3ina i mf timer 3 input a p8.1 46 48 t1inb i mf timer 1 input b p8.2 45 47 int1 i external interrupt 1 t1outa o mf timer 1 output a p8.3 44 46 int3 i external interrupt 3 t1outb o mf timer 1 output b p8.4 43 45 t1ina i mf timer 1 input a wait i external wait input wdout o watchdog timer output p8.5 42 44 t3inb i mf timer 3 input b p8.6 41 43 int7 i external interrupt 7 t3outa o mf timer 3 output a p8.7 40 42 nmi i non-maskable interrupt t3outb o mf timer 3 output b port name general purpose i/o pin no. alternate functions tqfp pqfp 9
17/190 st90158 - general description note 1) not present on st90135 p9.0 all ports useable for general pur- pose i/o (input, output or bidirec- tional) 23 25 s1out o sci1 serial output 1) p9.1 24 26 t0outb o mf timer 0 output b 1) s1in i sci1 serial input 1) p9.2 25 27 clk1out o sci1 byte sync clock output 1) tx1ckin i sci1 transmit clock input 1) p9.4 26 28 s0out o sci0 serial output rx1ckin o sci1 receive clock input 1) p9.5 27 29 s0in i sci0 serial input p9.6 28 30 int2 i external interrupt 2 sck o spi serial clock p9.7 29 31 int6 i external interrupt 6 sdo o spi serial data out port name general purpose i/o pin no. alternate functions tqfp pqfp 9
18/190 st90158 - device architecture 2 device architecture 2.1 core architecture the st9+ core or central processing unit (cpu) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats; 14 address- ing modes are available. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit in- terrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture affords a high de- gree of pipelining and parallel operation, thus mak- ing the st9+ family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources. 2.2 memory spaces there are two separate memory spaces: the register file, which comprises 240 8-bit registers, arranged as 15 groups (group 0 to e), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in group f, which hold data and control bits for the on-chip peripherals and i/os. a single linear memory space accommodating both program and data. all of the physically sep- arate memory areas, including the internal rom, internal ram and external memory are mapped in this common address space. the total ad- dressable memory space of 4 mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 seg- ments of 64 kbytes. each segment is further subdivided into four pages of 16 kbytes, as illus- trated in figure 5. a memory management unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instruc- tions. 2.2.1 register file the register file consists of (see figure 6): 224 general purpose registers (group 0 to d, registers r0 to r223) 6 system registers in the system group (group e, registers r224 to r239) up to 64 pages, depending on device configura- tion, each containing up to 16 registers, mapped to group f (r240 to r255), see figure 7. figure 5. single program and data memory address space 3fffffh 3f0000h 3effffh 3e0000h 20ffffh 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h 8 7 6 5 4 3 2 1 0 63 62 2 1 0 address 16k pages 64k segments up to 4 mbytes data code 255 254 253 252 251 250 249 248 247 9 10 11 21ffffh 210000h 133 134 135 33 reserved 132 9
19/190 st90158 - device architecture memory spaces (cont'd) figure 6. register groups figure 7. page pointer for group f mapping figure 8. addressing the register file f e d c b a 9 8 7 6 5 4 3 paged registers system registers 2 1 0 00 15 255 240 239 224 223 va00432 up to 64 pages general registers purpose 224 page 63 page 5 page 0 page pointer r255 r240 r224 r0 va00433 r234 register file system registers group d group b group c (1100) (0011) r192 r207 255 240 239 224 223 f e d c b a 9 8 7 6 5 4 3 2 1 0 15 vr000118 00 r195 r195 (r0c3h) paged registers 9
20/190 st90158 - device architecture memory spaces (cont'd) 2.2.2 register addressing register file registers, including group f paged registers (but excluding group d), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus r231, re7h and r11100111b represent the same register (see figure 8). group d registers can only be ad- dressed in working register mode. note that an upper case a r o is used to denote this direct addressing mode. working registers certain types of instruction require that registers be specified in the form a rx o, where x is in the range 0 to 15: these are known as working regis- ters. note that a lower case a r o is used to denote this in- direct addressing mode. two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working reg- isters. these groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. this tech- nique is described in more detail in section 2.3.3 register pointing techniques, and illustrated in figure 9 and in figure 10. system registers the 16 registers in group e (r224 to r239) are system registers and may be addressed using any of the register addressing modes. these registers are described in greater detail in section 2.3 sys- tem registers. paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these are addressed us- ing any register addressing mode, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. therefore if the page pointer, r234, is set to 5, the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). these paged registers hold data and control infor- mation relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9+ devices. the number of these reg- isters therefore depends on the peripherals which are present in the specific st9+ family device. in other words, pages only exist if the relevant pe- ripheral is present. table 3. register file organization hex. address decimal address function register file group f0-ff 240-255 paged registers group f e0-ef 224-239 system registers group e d0-df 208-223 general purpose registers group d c0-cf 192-207 group c b0-bf 176-191 group b a0-af 160-175 group a 90-9f 144-159 group 9 80-8f 128-143 group 8 70-7f 112-127 group 7 60-6f 96-111 group 6 50-5f 80-95 group 5 40-4f 64-79 group 4 30-3f 48-63 group 3 20-2f 32-47 group 2 10-1f 16-31 group 1 00-0f 00-15 group 0 9
21/190 st90158 - device architecture 2.3 system registers the system registers are listed in table 4. they are used to perform all the important system set- tings. their purpose is described in the following pages. refer to the chapter dealing with i/o for a description of the port[5:0] data registers. table 4. system registers (group e) 2.3.1 central interrupt control register please refer to the ointerrupto chapter for a de- tailed description of the st9 interrupt philosophy. central interrupt control register (cicr) r230 - read/write register group: e (system) reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable . this bit is the global counter enable of the multi- function timers. the gcen bit is anded with the ce bit in the tcr register (only in devices featur- ing the mft multifunction timer) in order to enable the timers when both bits are set. this bit is set af- ter the reset cycle. note: if an mft is not included in the st9 device, then this bit has no effect. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when a top level inter- rupt request is recognized. this bit can also be set by software to simulate a top level interrupt request. 0: no top level interrupt pending 1: top level interrupt pending bit 5 = tli : top level interrupt bit . 0: top level interrupt is acknowledged depending on the tlnm bit in the nicr register. 1: top level interrupt is acknowledged depending on the ien and tlnm bits in the nicr register (described in the interrupt chapter). bit 4 = ien : interrupt enable . this bit is cleared by interrupt acknowledgement, and set by interrupt return ( iret ). ien is modified implicitly by iret , ei and di instructions or by an interrupt acknowledge cycle. it can also be explic- itly written by the user, but only when no interrupt is pending. therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the cicr register. 0: disable all interrupts except top level interrupt. 1: enable interrupts bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software to select the arbitration mode. 0: concurrent mode 1: nested mode. bit 2:0 = cpl[2:0] : current priority level . these three bits record the priority level of the rou- tine currently running (i.e. the current priority lev- el, cpl). the highest priority level is represented by 000, and the lowest by 111. the cpl bits can be set by hardware or software and provide the reference according to which subsequent inter- rupts are either left pending or are allowed to inter- rupt the current interrupt service routine. when the current interrupt is replaced by one of a higher pri- ority, the current priority value is automatically stored until required in the nicr register. r239 (efh) ssplr r238 (eeh) ssphr r237 (edh) usplr r236 (ech) usphr r235 (ebh) mode register r234 (eah) page pointer register r233 (e9h) register pointer 1 r232 (e8h) register pointer 0 r231 (e7h) flag register r230 (e6h) central int. cntl reg r229 (e5h) port5 data reg. r228 (e4h) port4 data reg. r227 (e3h) port3 data reg. r226 (e2h) port2 data reg. r225 (e1h) port1 data reg. r224 (e0h) port0 data reg. 70 gce n tlip tli ien iam cpl2 cpl1 cpl0 9
22/190 st90158 - device architecture system registers (cont'd) 2.3.2 flag register the flag register contains 8 flags which indicate the cpu status. during an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the cpu to its original status. this occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. flag register (flagr) r231- read/write register group: e (system) reset value: 0000 0000 (00h ) bit 7 = c : carry flag . the carry flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate ( rrc, rrcw, rlc, rlcw, ror, rol ), decimal adjust ( da ), multiply and divide ( mul, div, divws ). when set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). the carry flag can be set by the set carry flag ( scf ) instruction, cleared by the reset carry flag ( rcf ) instruction, and complemented by the com- plement carry flag ( ccf ) instruction. bit 6 = z: zero flag . the zero flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate (rrc , rrcw, rlc, rlcw, ror, rol) , decimal adjust ( da ), multiply and divide ( mul, div, divws ), logical ( and, andw, or, orw, xor, xorw, cpl ), increment and decrement ( inc, incw, dec, decw ), test ( tm, tmw, tcm, tcmw, btset ). in most cases, the zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. bit 5 = s : sign flag . the sign flag is affected by the same instructions as the zero flag. the sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. bit 4 = v : overflow flag . the overflow flag is affected by the same instruc- tions as the zero and sign flags. when set, the overflow flag indicates that a two's- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in two's-complement notation. bit 3 = da : decimal adjust flag . the da flag is used for bcd arithmetic. since the algorithm for correcting bcd operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent decimal adjust ( da ) operation can perform its function correctly. the da flag cannot normally be used as a test condi- tion by the programmer. bit 2 = h : half carry flag. the h flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two bcd digits. the h flag is used by the decimal adjust ( da ) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct bcd result. like the da flag, this flag is not normally accessed by the user. bit 1 = reserved bit (must be 0). bit 0 = dp : data/program memory flag . this bit indicates the memory area addressed. its value is affected by the set data memory ( sdm ) and set program memory ( spm ) instructions. re- fer to the memory management unit for further de- tails. 70 c z s v da h - dp 9
23/190 st90158 - device architecture system registers (cont'd) if the bit is set, data is accessed using the data pointers (dprs registers), otherwise it is pointed to by the code pointer (csr register); therefore, the user initialization routine must include a sdm instruction. note that code is always pointed to by the code pointer (csr). note: in the st9+, the dp flag is only for compat- ibility with software developed for the first genera- tion of st9 devices. with the single memory ad- dressing space, its use is now redundant. it must be kept to 1 with a sdm instruction at the beginning of the program to ensure a normal use of the differ- ent memory pointers. 2.3.3 register pointing techniques two registers within the system register group, are used as pointers to the working registers. reg- ister pointer 0 (r232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with register pointer 1 (r233), to point to two separate 8-register spaces. for the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. the values specified with the set register pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. the set register pointer instructions srp , srp0 and srp1 automatically inform the cpu whether the register file is to operate in single 16-register mode or in twin 8-register mode. the srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. there is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. the block number should always be an even number in single 16-register mode. the 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. thus: srp #3 will be interpreted as srp #2 and will al- low using r16 ..r31 as r0 .. r15. in single 16-register mode, the working registers are referred to as r0 to r15 . in twin 8-register mode, registers r0 to r7 are in the block pointed to by rp0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by rp1 (by means of the srp1 instruction). caution : group d registers can only be accessed as working registers using the register pointers, or by means of the stack pointers. they cannot be addressed explicitly in the form a rxxx o. 9
24/190 st90158 - device architecture system registers (cont'd) pointer 0 register (rp0) r232 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bit 7:3 = rg[4:0] : register group number. these bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. in single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bit 1:0: reserved. forced by hardware to zero. pointer 1 register (rp1) r233 - read/write register group: e (system) reset value: xxxx xx00 (xxh) this register is only used in the twin register point- ing mode. when using the single register pointing mode, or when using only one of the twin register groups, the rp1 register must be considered as reserved and may not be used as a general purpose register. bit 7:3 = rg[4:0]: register group number. these bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 instruc- tion, to which r8 to r15 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bit 1:0: reserved. forced by hardware to zero. 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 9
25/190 st90158 - device architecture system registers (cont'd) figure 9. pointing to a single group of 16 registers figure 10. pointing to two groups of 8 registers 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group regist er file register pointer 0 srp #2 set by: instruction points to: group 1 addressed by block 2 r15 r0 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number regist er group register file register pointe r 0 srp0 #2 set by: instructions point to: group 1 addressed by block 2 & regist er pointe r 1 srp1 #7 & group 3 addressed by block 7 r7 r0 r15 r8 9
26/190 st90158 - device architecture system registers (cont'd) 2.3.4 paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9+ devices. the number of these registers depends on the pe- ripherals present in the specific st9 device. in oth- er words, pages only exist if the relevant peripher- al is present. the paged registers are addressed using the nor- mal register addressing modes, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. thus the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). warning: during an interrupt, the ppr register is not saved automatically in the stack. if needed, it should be saved/restored by the user within the in- terrupt routine. page pointer register (ppr) r234 - read/write register group: e (system) reset value: xxxx xx00 (xxh ) bit 7:2 = pp[5:0] : page pointer . these bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. bit 1:0: reserved. forced by hardware to 0. 2.3.5 mode register the mode register allows control of the following operating parameters: selection of internal or external system and user stack areas, management of the clock frequency, enabling of bus request and wait signals when interfacing to external memory. mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7 = ssp : system stack pointer . this bit selects an internal or external system stack area. 0: external system stack area, in memory space. 1: internal system stack area, in the register file (reset state). bit 6 = usp : user stack pointer . this bit selects an internal or external user stack area. 0: external user stack area, in memory space. 1: internal user stack area, in the register file (re- set state). bit 5 = div2 : oscin clock divided by 2 . this bit controls the divide-by-2 circuit operating on oscin. 0: clock divided by 1 1: clock divided by 2 bit 4:2 = prs[2:0] : cpuclk prescaler . these bits load the prescaler division factor for the internal clock (intclk). the prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. refer to the reset and clock control chapter for further information. bit 1 = brqen : bus request enable . 0: external memory bus request disabled 1: external memory bus request enabled on the breq pin (where available). bit 0 = himp : high impedance enable . when any of ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as address and data lines to interface external memory, these lines and the memory interface control lines (as, 70 pp5 pp4 pp3 pp2 pp1 pp0 0 0 70 ssp usp div2 prs2 prs1 prs0 brqen himp 9
27/190 st90158 - device architecture system registers (cont'd) ds, r/w) can be forced into the high impedance state by setting the himp bit. when this bit is reset, it has no effect. setting the himp bit is recommended for noise re- duction when only internal memory is used. if port 1 and/or 2 are declared as an address and as an i/o port (for example: p10... p14 = address, and p15... p17 = i/o), the himp bit has no effect on the i/o lines. 2.3.6 stack pointers two separate, double-register stack pointers are available: the system stack pointer and the user stack pointer, both of which can address registers or memory. the stack pointers point to the abottomo of the stacks which are filled using the push commands and emptied using the pop commands. the stack pointer is automatically pre-decremented when data is apushedo in and post-incremented when data is apoppedo out. the push and pop commands used to manage the system stack may be addressed to the user stack by adding the suffix a uo . to use a stack in- struction for a word, the suffix a wo is added. these suffixes may be combined. when bytes (or words) are apoppedo out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. thus, when data is apoppedo from a stack area, the stack con- tents remain unchanged. note: instructions such as: pushuw rr236 or pushw rr238, as well as the corresponding pop instructions (where r236 & r237, and r238 & r239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. system stack the system stack is used for the temporary stor- age of system and/or control data, such as the flag register and the program counter. the following automatically push data onto the system stack: interrupts when entering an interrupt, the pc and the flag register are pushed onto the system stack. if the encsr bit in the emr2 register is set, then the code segment register is also pushed onto the system stack. subroutine calls when a call instruction is executed, only the pc is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the pc and the code segment register are pushed onto the system stack. link instruction the link or linku instructions create a c lan- guage stack frame of user-defined length in the system or user stack. all of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. user stack the user stack provides a totally user-controlled stacking area. the user stack pointer consists of two registers, r236 and r237, which are both used for address- ing a stack in memory. when stacking in the reg- ister file, the user stack pointer high register, r236, becomes redundant but must be consid- ered as reserved. stack pointers both system and user stacks are pointed to by double-byte stack pointers. stacks may be set up in ram or in the register file. only the lower byte will be required if the stack is in the register file. the upper byte must then be considered as re- served and must not be used as a general purpose register. the stack pointer registers are located in the sys- tem group of the register file, this is illustrated in table 4. stack location care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the register file as a stacking area. group d is a good location for a stack in the reg- ister file, since it is the highest available area. the stacks may be located anywhere in the first 14 groups of the register file (internal stacks) or in ram (external stacks). note . stacks must not be located in the paged register group or in the system register group. 9
28/190 st90158 - device architecture system registers (cont'd) user stack pointer high register (usphr) r236 - read/write register group: e (system) reset value: undefined user stack pointer low register (usplr) r237 - read/write register group: e (system) reset value: undefined figure 11. internal stack mode system stack pointer high register (ssphr) r238 - read/write register group: e (system) reset value: undefined system stack pointer low register (ssplr) r239 - read/write register group: e (system) reset value: undefined figure 12. external stack mode 70 usp1 5 usp1 4 usp1 3 usp1 2 usp1 1 usp1 0 usp9 usp8 70 usp7 usp6 usp5 usp4 usp3 usp2 usp1 usp0 f e d 4 3 2 1 0 regist er file stack pointer (low) points to: stack 70 ssp1 5 ssp1 4 ssp1 3 ssp1 2 ssp1 1 ssp1 0 ssp9 ssp8 70 ssp7 ssp6 ssp5 ssp4 ssp3 ssp2 ssp1 ssp0 f e d 4 3 2 1 0 register file stack pointer (low) point to: stack memory stack pointer (high) & 9
29/190 st90158 - device architecture 2.4 memory organization code and data are accessed within the same line- ar address space. all of the physically separate memory areas, including the internal rom, inter- nal ram and external memory are mapped in a common address space. the st9+ provides a total addressable memory space of 4 mbytes. this address space is ar- ranged as 64 segments of 64 kbytes; each seg- ment is again subdivided into four 16 kbyte pages. the mapping of the various memory areas (inter- nal ram or rom, external memory) differs from device to device. each 64-kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 kbytes, the remaining locations in the 64-kbyte segment are not used (reserved). refer to the register and memory map chapter for more details on the memory map. 9
30/190 st90158 - device architecture 2.5 memory management unit the cpu core includes a memory management unit (mmu) which must be programmed to per- form memory accesses (even if external memory is not used). the mmu is controlled by 7 registers and 2 bits (encsr and dprrem) present in emr2, which may be written and read by the user program. these registers are mapped within group f, page 21 of the register file. the 7 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (dpr[3:0]), and a second group of three 6-bit registers (csr, isr, and dmasr). the first group is used to extend the address during data memory access (dpr[3:0]). the second is used to manage program and data memory ac- cesses during code execution (csr), interrupts service routines (isr or csr), and dma trans- fers (dmasr or isr). figure 13. page 21 registers dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu em page 21 mmu mmu bit dprrem=0 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 1 dpr0 bit dprrem=1 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers (default setting) 9
31/190 st90158 - device architecture 2.6 address space extension to manage 4 mbytes of addressing space it is necessary to have 22 address bits. the mmu adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. there are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed. 2.6.1 addressing 16-kbyte pages this extension mode is implicitly used to address data memory space if no dma is being performed. the data memory space is divided into 4 pages of 16 kbytes. each one of the four 8-bit registers (dpr[3:0], data page registers) selects a differ- ent 16-kbyte page. the dpr registers allow ac- cess to the entire memory space which contains 256 pages of 16 kbytes. data paging is performed by extending the 14 lsb of the 16-bit address with the contents of a dpr register. the two msbs of the 16-bit address are interpreted as the identification number of the dpr register to be used. therefore, the dpr registers are involved in the following virtual address rang- es: dpr0: from 0000h to 3fffh; dpr1: from 4000h to 7fffh; dpr2: from 8000h to bfffh; dpr3: from c000h to ffffh. the contents of the selected dpr register specify one of the 256 possible data memory pages. this 8-bit data page number, in addition to the remain- ing 14-bit page offset address forms the physical 22-bit address (see figure 14). a dpr register cannot be modified via an address- ing mode that uses the same dpr register. for in- stance, the instruction apopw dpr0o is legal only if the stack is kept either in the register file or in a memory location above 8000h, where dpr2 and dpr3 are used. otherwise, since dpr0 and dpr1 are modified by the instruction, unpredicta- ble behaviour could result. figure 14. addressing via dpr[3:0] dpr0 dpr1 dpr2 dpr3 00 01 10 11 16-bit virtual address 22-bit physical address 8 bits mmu registers 2 m sb 14 lsb 9
32/190 st90158 - device architecture address space extension (cont'd) 2.6.2 addressing 64-kbyte segments this extension mode is used to address data memory space during a dma and program mem- ory space during any code execution (normal code and interrupt routines). three registers are used: csr, isr, and dmasr. the 6-bit contents of one of the registers csr, isr, or dmasr define one out of 64 memory seg- ments of 64 kbytes within the 4 mbytes address space. the register contents represent the 6 msbs of the memory address, whereas the 16 lsbs of the address (intra-segment address) are given by the virtual 16-bit address (see figure 15). 2.7 mmu registers the mmu uses 7 registers mapped into group f, page 21 of the register file and 2 bits of the emr2 register. most of these registers do not have a default value after reset. 2.7.1 dpr[3:0]: data page registers the dpr[3:0] registers allow access to the entire 4 mbyte memory space composed of 256 pages of 16 kbytes. 2.7.1.1 data page register relocation if these registers are to be used frequently, they may be relocated in register group e, by program- ming bit 5 of the emr2-r246 register in page 21. if this bit is set, the dpr[3:0] registers are located at r224-227 in place of the port 0-3 data registers, which are re-mapped to the default dpr's loca- tions: r240-243 page 21. data page register relocation is illustrated in fig- ure 13. figure 15. addressing via csr, isr, and dmasr fetching program data memory fetching interrupt instruction accessed in dma instruction or dma access to program memory 16-bit virtual address 22-bit physical address 6 bits mmu registers csr isr dmasr 123 1 2 3 9
33/190 st90158 - device architecture mmu registers (cont'd) data page register 0 (dpr0) r240 - read/write register page: 21 reset value: undefined this register is relocated to r224 if emr2.5 is set. bit 7:0 = dpr0_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr0 register is used when addressing the virtual address range 0000h-3fffh. data page register 1 (dpr1) r241 - read/write register page: 21 reset value: undefined this register is relocated to r225 if emr2.5 is set. bit 7:0 = dpr1_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr1 register is used when addressing the virtual address range 4000h-7fffh. data page register 2 (dpr2) r242 - read/write register page: 21 reset value: undefined this register is relocated to r226 if emr2.5 is set. bit 7:0 = dpr2_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr2 register is involved when the virtual address is in the range 8000h-bfffh. data page register 3 (dpr3) r243 - read/write register page: 21 reset value: undefined this register is relocated to r227 if emr2.5 is set. bit 7:0 = dpr3_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr3 register is involved when the virtual address is in the range c000h-ffffh. 70 dpr0 _7 dpr0 _6 dpr0 _5 dpr0 _4 dpr0 _3 dpr0 _2 dpr0 _1 dpr0 _0 70 dpr1 _7 dpr1 _6 dpr1 _5 dpr1 _4 dpr1 _3 dpr1 _2 dpr1 _1 dpr1 _0 70 dpr2 _7 dpr2 _6 dpr2 _5 dpr2 _4 dpr2 _3 dpr2 _2 dpr2 _1 dpr2 _0 70 dpr3 _7 dpr3 _6 dpr3 _5 dpr3 _4 dpr3 _3 dpr3 _2 dpr3 _1 dpr3 _0 9
34/190 st90158 - device architecture mmu registers (cont'd) 2.7.2 csr: code segment register this register selects the 64-kbyte code segment being used at run-time to access instructions. it can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp ). only the 6 lsbs of the csr register are imple- mented, and bits 6 and 7 are reserved. the csr register allows access to the entire memory space, divided into 64 segments of 64 kbytes. to generate the 22-bit program memory address, the contents of the csr register is directly used as the 6 msbs, and the 16-bit virtual address as the 16 lsbs. note: the csr register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). it is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. code segment register (csr) r244 - read/write register page: 21 reset value: 0000 0000 (00h) bit 7:6 = reserved, keep in reset state. bit 5:0 = csr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the code being executed. these bits are used as the most significant address bits (a21-16). 2.7.3 isr: interrupt segment register interrupt segment register (isr) r248 - read/write register page: 21 reset value: undefined isr and encsr bit (emr2 register) are also de- scribed in the chapter relating to interrupts, please refer to this description for further details. bit 7:6 = reserved, keep in reset state. bit 5:0 = isr_[5:0] : these bits define the 64-kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and dma transfers (when the ps bit of the dapr register is reset). these bits are used as the most significant address bits (a21-16). the isr is used to extend the address space in two cases: whenever an interrupt occurs: isr points to the 64-kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. see also the interrupts chapter. during dma transactions between the peripheral and memory when the ps bit of the dapr regis- ter is reset : isr points to the 64 k-byte memory segment that will be involved in the dma trans- action. 2.7.4 dmasr: dma segment register dma segment register (dmasr) r249 - read/write register page: 21 reset value: undefined bit 7:6 = reserved, keep in reset state. bit 5:0 = dmasr_[5:0] : these bits define the 64- kbyte memory segment (among 64) used when a dma transaction is performed between the periph- eral's data register and memory, with the ps bit of the dapr register set. these bits are used as the most significant address bits (a21-16). if the ps bit is reset, the isr register is used to extend the ad- dress. 70 00 csr_ 5 csr_ 4 csr_ 3 csr_ 2 csr_ 1 csr_ 0 70 0 0 isr_5 isr_4 isr_3 isr_2 isr_1 isr_0 70 00 dma sr_5 dma sr_4 dma sr_3 dma sr_2 dma sr_1 dma sr_0 9
35/190 st90158 - device architecture mmu registers (cont'd) figure 16. memory addressing scheme (example) 3fffffh 294000h 240000h 23ffffh 20c000h 200000h 1fffffh 040000h 03ffffh 030000h 020000h 010000h 00c000h 000000h dmasr isr csr dpr3 dpr2 dpr1 dpr0 4m bytes 16k 16k 16k 64k 64k 64k 16k 9
36/190 st90158 - device architecture 2.8 mmu usage 2.8.1 normal program execution program memory is organized as a set of 64- kbyte segments. the program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps , calls and rets instructions, which automatically modify the csr, must be used to jump across segment boundaries. writing to the csr is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. this could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. writing to the csr is allowed when it is not be- ing used, i.e during an interrupt service routine if encsr is reset. note that a routine must always be called in the same way, i.e. either always with call or always with calls , depending on whether the routine ends with ret or rets . this means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-kbyte seg- ment, then calls / rets should be used. in typical microcontroller applications, less than 64 kbytes of ram are used, so the four data space pages are normally sufficient, and no change of dpr[3:0] is needed during program execution. it may be useful however to map part of the rom into the data space if it contains strings, tables, bit maps, etc. if there is to be frequent use of paging, the user can set bit 5 (dprrem) in register r246 (emr2) of page 21. this swaps the location of registers dpr[3:0] with that of the data registers of ports 0- 3. in this way, dpr registers can be accessed without the need to save/set/restore the page pointer register. port registers are therefore moved to page 21. applications that require a lot of paging typically use more than 64 kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 interrupts the isr register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. when an interrupt occurs, the cpu behaves in one of 2 ways, depending on the value of the enc- sr bit in the emr2 register (r246 on page 21). if this bit is reset (default condition), the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, the isr is used instead of the csr, and the interrupt stack frame is kept exactly as in the original st9 (only the pc and flags are pushed). this avoids the need to save the csr on the stack in the case of an interrupt, ensuring a fast interrupt response time. the drawback is that it is not possible for an interrupt service routine to perform segment calls / jps : these instructions would update the csr, which, in this case, is not used (isr is used instead). the code size of all interrupt service rou- tines is thus limited to 64 kbytes. if, instead, bit 6 of the emr2 register is set, the isr is used only to point to the interrupt vector ta- ble and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and the flags, and then the csr is loaded with the isr. in this case, an iret will also restore the csr from the stack. this approach lets interrupt service routines access the whole 4-mbyte address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save the csr on the stack. compatibility with the original st9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. data memory mapping is independent of the value of bit 6 of the emr2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the st9. if the interrupt service routine needs to access additional data memory, it must save one (or more) of the dprs, load it with the needed memory page and restore it before completion. 2.8.3 dma depending on the ps bit in the dapr register (see dma chapter) dma uses either the isr or the dmasr for memory accesses: this guarantees that a dma will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. unlike interrupts, dma transactions cannot save/restore paging registers, so a dedicated segment register (dmasr) has been created. having only one register of this kind means that all dma accesses should be pro- grammed in one of the two following segments: the one pointed to by the isr (when the ps bit of the dapr register is reset), and the one refer- enced by the dmasr (when the ps bit is set). 9
37/190 st90158 - register and memory map 3 register and memory map 3.1 memory configuration the program memory space of the st90135/158, 0/16/24/32/48/64/k bytes of directly addressable on-chip memory, is fully available to the user. the first 256 memory locations from address 0 to ffh hold the reset vector, the top-level (pseudo non-maskable) interrupt, the divide by zero trap routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. apart from this case no other part of the program memory has a predeter- mined function except segment 21h which is re- served for use by stmicroelectronics. 3.2 eprom programming the 65536 bytes of eprom memory of the st90e158 may be programmed by using the eprom programming boards (epb) or gang pro- grammers available from stmicroelectronics. eprom erasing the eprom of the windowed package of the st90e158 may be erased by exposure to ultra-vi- olet light. the erasure characteristic of the st90e158 is such that erasure begins when the memory is ex- posed to light with a wave lengths shorter than ap- proximately 4000?. it should be noted that sunlight and some types of fluorescent lamps have wave- lengths in the range 3000-4000?. it is thus recom- mended that the window of the st90e158 packag- es be covered by an opaque label to prevent unin- tentional erasure problems when testing the appli- cation in such an environment. the recommended erasure procedure of the eprom is the exposure to short wave ultraviolet light which have a wave-length 2537?. the inte- grated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 15w-sec/cm2. the erasure time with this dosage is approximate- ly 30 minutes using an ultraviolet lamp with 12000mw/cm2 power rating. the st90e158 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure. table 5. first 6 bytes of program space 0 address high of power on reset routine 1 address low of power on reset routine 2 address high of divide by zero trap subroutine 3 address low of divide by zero trap subroutine 4 address high of top level interrupt routine 5 address low of top level interrupt routine 9
38/190 st90158 - register and memory map figure 17. interrupt vector table user isr program memory power-on reset divide-b y-zero top level int. lo lo lo hi hi hi 000000h user main program user top level isr user divide-by -zero isr 0000ffh vector table isr addres s even odd int. vector register lo hi registe r file r240 r239 f page registe rs 000002h 000004h 9
39/190 st90158 - register and memory map 3.3 memory map figure 18. memory map 010000h 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes 200000h 22ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes external memory reserved external memory segments 21h and 22h 128 kbytes (external rom on 20ffffh 230000h 3fffffh lower memory (usually rom/eprom mapped upper memory (usually ram mapped 210000h note: the total amount of directly addressable external memory is 64 kbytes. in segment 1) in segment 23h) 1fffffh 000000 h 003fffh rom 16 kbytes internal 24 kbytes 32 kbytes 48 kbytes 64 kbytes 00ffffh 007fffh 00bfffh 00ffffh ram 512 bytes internal 768 bytes 1 kbytes 1.5 kbytes 2 kbytes 20f800h 20fa00h 20fc00h 20fd00h 20fe00h 20ffffh 64 kbytes segment 0 64 kbytes segment 20h internal rom/eprom romless devices) 9
40/190 st90158 - register and memory map 3.4 st90158/135 register map the following pages contain a list of st90158/135 registers, grouped by peripheral or function. be very careful to correctly program both: the set of registers dedicated to a particular function or peripheral. registers common to other functions. in particular, double-check that any registers with aundefinedo reset values have been correct- ly initialised. warning : note that in the eivr and each ivr reg- ister, all bits are significant. take care when defin- ing base vector addresses that entries in the inter- rupt vector table do not overlap. table 6. common registers function or peripheral common registers sci, mft cicr + nicr + dma registers + i/o port registers adc cicr + nicr + i/o port registers spi, wdt, stim cicr + nicr + external interrupt registers + i/o port registers i/o ports i/o port registers + moder external interrupt interrupt registers + i/o port registers rccu interrupt registers + moder 9
41/190 st90158 - register and memory map table 7. group f pages resources available on the st90158/st90135 devices: (*) st90158/st90e158 only. not present on st90135. register page 0 2 3 8 9 10111213212425 43 5563 r255 res. res. port 7 mft1 res. mft0 (*) res. mft3 res. res. sci0 sci1 (*) port 9 res. a/d r254 spi r253 r252 wcr r251 wdt port 6 port 8 r250 port 2 r249 mmu r248 mft r247 ext int res. res. mft1 mft3 res. res. r246 port 1 port 5 ext mi rccu r245 res. r244 mmu r243 res. res. mft0 (*) stim res. r242 port 0 port 4 rccu r241 res. res. r240 rccu 9
42/190 st90158 - register and memory map table 8. detailed register map page (decimal) block reg. no. register name description reset value hex. n/a core r230 cicr central interrupt control register 87 r231 flagr flag register 00 r232 rp0 pointer 0 register xx r233 rp1 pointer 1 register xx r234 ppr page pointer register xx r235 moder mode register e0 r236 usphr user stack pointer high register xx r237 usplr user stack pointer low register xx r238 ssphr system stack pointer high reg. xx r239 ssplr system stack pointer low reg. xx i/o port 5:4,2:0 r224 p0dr port 0 data register ff r225 p1dr port 1 data register ff r226 p2dr port 2 data register ff r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff 0 int r242 eitr external interrupt trigger register 00 r243 eipr external interrupt pending reg. 00 r244 eimr external interrupt mask-bit reg. 00 r245 eiplr external interrupt priority level reg. ff r246 eivr external interrupt vector register x6 r247 nicr nested interrupt control 00 wdt r248 wdthr watchdog timer high register ff r249 wdtlr watchdog timer low register ff r250 wdtpr watchdog timer prescaler reg. ff r251 wdtcr watchdog timer control register 12 r252 wcr wait control register 7f spi r253 spidr spi data register xx r254 spicr spi control register 00 2 i/o port 0 r240 p0c0 port 0 configuration register 0 00 r241 p0c1 port 0 configuration register 1 00 r242 p0c2 port 0 configuration register 2 00 i/o port 1 r244 p1c0 port 1 configuration register 0 00 r245 p1c1 port 1 configuration register 1 00 r246 p1c2 port 1 configuration register 2 00 i/o port 2 r248 p2c0 port 2 configuration register 0 ff r249 p2c1 port 2 configuration register 1 00 r250 p2c2 port 2 configuration register 2 00 9
43/190 st90158 - register and memory map 3 i/o port 4 r240 p4c0 port 4 configuration register 0 ff r241 p4c1 port 4 configuration register 1 00 r242 p4c2 port 4 configuration register 2 00 i/o port 5 r244 p5c0 port 5 configuration register 0 ff r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 i/o port 6 r248 p6c0 port 6 configuration register 0 ff r249 p6c1 port 6 configuration register 1 00 r250 p6c2 port 6 configuration register 2 00 r251 p6dr port 6 data register ff i/o port 7 r252 p7c0 port 7 configuration register 0 00/ff r253 p7c1 port 7 configuration register 1 00/00 r254 p7c2 port 7 configuration register 2 00/00 r255 p7dr port 7 data register ff page (decimal) block reg. no. register name description reset value hex. 9
44/190 st90158 - register and memory map 8 mft1 r240 reg0hr1 capture load register 0 high xx r241 reg0lr1 capture load register 0 low xx r242 reg1hr1 capture load register 1 high xx r243 reg1lr1 capture load register 1 low xx r244 cmp0hr1 compare 0 register high 00 r245 cmp0lr1 compare 0 register low 00 r246 cmp1hr1 compare 1 register high 00 r247 cmp1lr1 compare 1 register low 00 r248 tcr1 timer control register 0x r249 tmr1 timer mode register 00 r250 icr1 external input control register 0x r251 prsr1 prescaler register 00 r252 oacr1 output a control register xx r253 obcr1 output b control register xx r254 flagr1 flags register 00 r255 idmr1 interrupt/dma mask register 00 9 r244 dcpr0 dma counter pointer register xx r245 dapr0 dma address pointer register xx r246 ivr0 interrupt vector register xx r247 idcr0 interrupt/dma control register c7 mft0,1 r248 iocr i/o connection register fc mft0 (*) r240 dcpr1 dma counter pointer register xx r241 dapr1 dma address pointer register xx r242 ivr1 interrupt vector register xx r243 idcr1 interrupt/dma control register c7 10 r240 reg0hr0 capture load register 0 high xx r241 reg0lr0 capture load register 0 low xx r242 reg1hr0 capture load register 1 high xx r243 reg1lr0 capture load register 1 low xx r244 cmp0hr0 compare 0 register high 00 r245 cmp0lr0 compare 0 register low 00 r246 cmp1hr0 compare 1 register high 00 r247 cmp1lr0 compare 1 register low 00 r248 tcr0 timer control register 0x r249 tmr0 timer mode register 00 r250 icr0 external input control register 0x r251 prsr0 prescaler register 00 r252 oacr0 output a control register xx r253 obcr0 output b control register xx r254 flagr0 flags register 00 r255 idmr0 interrupt/dma mask register 00 page (decimal) block reg. no. register name description reset value hex. 9
45/190 st90158 - register and memory map 11 stim r240 sth counter high byte register ff r241 stl counter low byte register ff r242 stp standard timer prescaler register ff r243 stc standard timer control register 14 12 mft3 r240 reg0hr1 capture load register 0 high xx r241 reg0lr1 capture load register 0 low xx r242 reg1hr1 capture load register 1 high xx r243 reg1lr1 capture load register 1 low xx r244 cmp0hr1 compare 0 register high 00 r245 cmp0lr1 compare 0 register low 00 r246 cmp1hr1 compare 1 register high 00 r247 cmp1lr1 compare 1 register low 00 r248 tcr1 timer control register 0x r249 tmr1 timer mode register 00 r250 icr1 external input control register 0x r251 prsr1 prescaler register 00 r252 oacr1 output a control register xx r253 obcr1 output b control register xx r254 flagr1 flags register 00 r255 idmr1 interrupt/dma mask register 00 13 r244 dcpr0 dma counter pointer register xx r245 dapr0 dma address pointer register xx r246 ivr0 interrupt vector register xx r247 idcr0 interrupt/dma control register c7 21 mmu r240 dpr0 data page register 0 xx r241 dpr1 data page register 1 xx r242 dpr2 data page register 2 xx r243 dpr3 data page register 3 xx r244 csr code segment register 00 r248 isr interrupt segment register xx r249 dmasr dma segment register xx extmi r245 emr1 external memory register 1 80 r246 emr2 external memory register 2 0f page (decimal) block reg. no. register name description reset value hex. 9
46/190 st90158 - register and memory map 24 sci0 r240 rdcpr0 receiver dma transaction counter pointer xx r241 rdapr0 receiver dma source address pointer xx r242 tdcpr0 transmitter dma transaction counter pointer xx r243 tdapr0 transmitter dma destination address pointer xx r244 ivr0 interrupt vector register xx r245 acr0 address/data compare register xx r246 imr0 interrupt mask register x0 r247 isr0 interrupt status register xx r248 rxbr0 receive buffer register xx r248 txbr0 transmitter buffer register xx r249 idpr0 interrupt/dma priority register xx r250 chcr0 character configuration register xx r251 ccr0 clock configuration register 00 r252 brghr0 baud rate generator high reg. xx r253 brglr0 baud rate generator low register xx r254 sicr0 synchronous input control 03 r255 socr0 synchronous output control 01 25 sci1 (*) r240 rdcpr1 receiver dma transaction counter pointer xx r241 rdapr1 receiver dma source address pointer xx r242 tdcpr1 transmitter dma transaction counter pointer xx r243 tdapr1 transmitter dma destination address pointer xx r244 ivr1 interrupt vector register xx r245 acr1 address/data compare register xx r246 imr1 interrupt mask register x0 r247 isr1 interrupt status register xx r248 rxbr1 receive buffer register xx r248 txbr1 transmitter buffer register xx r249 idpr1 interrupt/dma priority register xx r250 chcr1 character configuration register xx r251 ccr1 clock configuration register 00 r252 brghr1 baud rate generator high reg. xx r253 brglr1 baud rate generator low register xx r254 sicr1 synchronous input control 03 r255 socr1 synchronous output control 01 43 i/o port 8 r248 p8c0 port 8 configuration register 0 00/03 r249 p8c1 port 8 configuration register 1 00/00 r250 p8c2 port 8 configuration register 2 00/00 r251 p8dr port 8 data register ff i/o port 9 r252 p9c0 port 9 configuration register 0 00/00 r253 p9c1 port 9 configuration register 1 00/00 r254 p9c2 port 9 configuration register 2 00/00 r255 p9dr port 9 data register ff page (decimal) block reg. no. register name description reset value hex. 9
47/190 st90158 - register and memory map (*) not present on st90135. note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. 55 rccu r240 clkctl clock control register 00 r242 clk_flag clock flag register 48, 28 or 08 r246 pllconf pll configuration register xx 63 ad0 r240 d0r0 channel 0 data register xx r241 d1r0 channel 1 data register xx r242 d2r0 channel 2 data register xx r243 d3r0 channel 3 data register xx r244 d4r0 channel 4 data register xx r245 d5r0 channel 5 data register xx r246 d6r0 channel 6 data register xx r247 d7r0 channel 7 data register xx r248 lt6r0 channel 6 lower threshold reg. xx r249 lt7r0 channel 7 lower threshold reg. xx r250 ut6r0 channel 6 upper threshold reg. xx r251 ut7r0 channel 7 upper threshold reg. xx r252 crr0 compare result register 0f r253 clr0 control logic register 00 r254 icr0 interrupt control register 0f r255 ivr0 interrupt vector register x2 page (decimal) block reg. no. register name description reset value hex. 9
48/190 st90158 - interrupts 4 interrupts 4.1 introduction the st9 responds to peripheral and external events through its interrupt channels. current pro- gram execution can be suspended to allow the st9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. if an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate interrupt service routine. the st9 cpu can receive requests from the fol- lowing sources: on-chip peripherals external pins top-level pseudo-non-maskable interrupt according to the on-chip peripheral features, an event occurrence can generate an interrupt re- quest which depends on the selected mode. up to eight external interrupt channels, with pro- grammable input trigger edge, are available. in ad- dition, a dedicated interrupt channel, set to the top-level priority, can be devoted either to the ex- ternal nmi pin (where available) to provide a non- maskable interrupt, or to the timer/watchdog. in- terrupt service routines are addressed through a vector table mapped in memory. figure 19. interrupt response n 4.2 interrupt vectoring the st9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the interrupt service routine automatically. when an interrupt request is acknowledged, the peripheral interrupt module provides, through its interrupt vector register (ivr), a vector to point into the vector table of locations containing the start addresses of the interrupt service routines (defined by the programmer). each peripheral has a specific ivr mapped within its register file pages. the interrupt vector table, containing the address- es of the interrupt service routines, is located in the first 256 locations of memory pointed to by the isr register, thus allowing 8-bit vector addressing. for a description of the isr register refer to the chapter describing the mmu. the user power on reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. the top level interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the interrupt segment register (isr). with one interrupt vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. the most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. note : the first 256 locations of the memory seg- ment pointed to by isr can contain program code. 4.2.1 divide by zero trap the divide by zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a divide by zero service routine is required. warning . although the divide by zero trap oper- ates as an interrupt, the flag register is not pushed onto the system stack automatically. as a result it must be regarded as a subroutine, and the service routine must end with the ret instruction (not iret ). normal program flow interrupt service routine iret instruction interrupt vr001833 clear pending bit 9
49/190 st90158 - interrupts 4.2.2 segment paging during interrupt routines the encsr bit in the emr2 register can be used to select between original st9 backward compati- bility mode and st9+ interrupt management mode. st9 backward compatibility mode (encsr = 0) if encsr is reset, the cpu works in original st9 compatibility mode. for the duration of the inter- rupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service routines is thus limited to 64k bytes. st9+ mode (encsr = 1) if encsr is set, isr is only used to point to the in- terrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the con- tents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service rou- tines to access the entire 4 mbytes of address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is differ- ent. 4.3 interrupt priority levels the st9 supports a fully programmable interrupt priority structure. nine priority levels are available to define the channel priority relationships: the on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. each channel has a 3- bit field, prl (priority level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). the 9th level (top level priority) is reserved for the timer/watchdog or the external pseudo non-maskable interrupt. an interrupt service routine at this level cannot be interrupted in any arbitration mode. its mask can be both maskable (tli) or non-maskable (tlnm). 4.4 priority level arbitration the 3 bits of cpl (current priority level) in the central interrupt control register contain the pri- ority of the currently running program (cpu priori- ty). cpl is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected arbitration mode. during every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an interrupt, each priority level is compared to all the other requests (interrupts or dma). if the highest priority request is an interrupt, its prl value must be strictly lower (that is, higher pri- ority) than the cpl value stored in the cicr regis- ter (r230) in order to be acknowledged. the top level interrupt overrides every other priority. 4.4.1 priority level 7 (lowest) interrupt requests at prl level 7 cannot be ac- knowledged, as this prl value (the lowest possi- ble priority) cannot be strictly lower than the cpl value. this can be of use in a fully polled interrupt environment. 4.4.2 maximum depth of nesting no more than 8 routines can be nested. if an inter- rupt routine at level n is being serviced, no other interrupts located at level n can interrupt it. this guarantees a maximum number of 8 nested levels including the top level interrupt request. 4.4.3 simultaneous interrupts if two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every st9 version, selects the channel encsr bit 0 1 mode st9 compatible st9+ pushed/popp ed registers pc, flagr pc, flagr, csr max. code size for interrupt service routine 64kb within 1 segment no limit across segments 9
50/190 st90158 - interrupts with the highest position in the chain, as shown in figure 9 table 9. daisy chain priority 4.4.4 dynamic priority level modification the main program and routines can be specifically prioritized. since the cpl is represented by 3 bits in a read/write register, it is possible to modify dy- namically the current priority value during program execution. this means that a critical section can have a higher priority with respect to other inter- rupt requests. furthermore it is possible to priori- tize even the main program execution by modify- ing the cpl during its execution. see figure 20 figure 20. example of dynamic priority level modification in nested mode 4.5 arbitration modes the st9 provides two interrupt arbitration modes: concurrent mode and nested mode. concurrent mode is the standard interrupt arbitration mode. nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. the iam control bit in the cicr register selects concurrent arbitration mode or nested arbitration mode. 4.5.1 concurrent mode this mode is selected when the iam bit is cleared (reset condition). the arbitration phase, performed during every instruction, selects the request with the highest priority level. the cpl value is not modified in this mode. start of interrupt routine the interrupt cycle performs the following steps: all maskable interrupt requests are disabled by clearing cicr.ien. the pc low byte is pushed onto system stack. the pc high byte is pushed onto system stack. if encsr is set, csr is pushed onto system stack. the flag register is pushed onto system stack. the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. end of interrupt routine the interrupt service routine must be ended with the iret instruction. the iret instruction exe- cutes the following operations: the flag register is popped from system stack. if encsr is set, csr is popped from system stack. the pc high byte is popped from system stack. the pc low byte is popped from system stack. all unmasked interrupts are enabled by setting the cicr.ien bit. if encsr is reset, csr is used instead of isr. normal program execution thus resumes at the in- terrupted instruction. all pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). note : in concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the cpl. no trace is kept of its value during the isr. if other requests are issued during the inter- rupt service routine, once the global cicr.ien is re-enabled, they will be acknowledged regardless of the interrupt service routine's priority. this may cause undesirable interrupt response sequences. highest position lowest position inta0 inta1 intb0 intb1 intc0 intc1 intd0 intd1 timer0 sci0 sci1 a/d timer3 timer1 int0/wdt int1 int2/spi int3 int4/stim int5 int6/rccu int7 6 5 4 7 priority level main cpl is set to 5 cpl=7 main int 6 cpl=6 int6 ei cpl is set to 7 cpl6 > cpl5: int6 pending interrupt 6 has priority level 6 by main program 9
51/190 st90158 - interrupts arbitration modes (cont'd) examples in the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. example 1 in the first example, (simplest case, figure 21) the ei instruction is not used within the interrupt serv- ice routines. this means that no new interrupt can be serviced in the middle of the current one. the interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes. figure 21. simple example of a sequence of interrupt requests with: - concurrent mode selected and - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 priority level of main int 5 int 2 int 3 int 4 main int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 interrupt request 9
52/190 st90158 - interrupts arbitration modes (cont'd) example 2 in the second example, (more complex, figure 22), each interrupt service routine sets interrupt enable with the ei instruction at the beginning of the routine. placed here, it minimizes response time for requests with a higher priority than the one being serviced. the level 2 interrupt routine (with the highest prior- ity) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be inter- rupted by the level 4 interrupt routine. when the level 4 interrupt routine is completed, the level 3 in- terrupt routine resumes and finally the level 2 inter- rupt routine. this results in the three interrupt serv- ice routines being executed in the opposite order of their priority. it is therefore recommended to avoid inserting the ei instruction in the interrupt service rou- tine in concurrent mode . use the ei instruc- tion only in nested mode. warning: if, in concurrent mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either encsr is set or csr=isr, otherwise the iret of the innermost in- terrupt will make the cpu use csr instead of isr before the outermost interrupt service routine is terminated, thus making the outermost routine fail. figure 22. complex example of a sequence of interrupt requests with: - concurrent mode selected - ien set to 1 during interrupt service routine execution 6 5 4 3 2 1 0 7 main int 5 int 2 int 3 int 4 int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrup t 2 has priority level 2 interrup t 3 has priority level 3 interrup t 4 has priority level 4 interrup t 5 has priority level 5 int 2 int 3 cpl = 7 cpl = 7 int 5 cpl = 7 main ei ei ei priority level of interrupt request ei 9
53/190 st90158 - interrupts arbitration modes (cont'd) 4.5.2 nested mode the difference between nested mode and con- current mode, lies in the modification of the cur- rent priority level (cpl) during interrupt process- ing. the arbitration phase is basically identical to con- current mode, however, once the request is ac- knowledged, the cpl is saved in the nested inter- rupt control register (nicr) by setting the nicr bit corresponding to the cpl value (i.e. if the cpl is 3, the bit 3 will be set). the cpl is then loaded with the priority of the re- quest just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being exe- cuted. start of interrupt routine the interrupt cycle performs the following steps: all maskable interrupt requests are disabled by clearing cicr.ien. cpl is saved in the special nicr stack to hold the priority level of the suspended routine. priority level of the acknowledged routine is stored in cpl, so that the next request priority will be compared with the one of the routine cur- rently being serviced. the pc low byte is pushed onto system stack. the pc high byte is pushed onto system stack. if encsr is set, csr is pushed onto system stack. the flag register is pushed onto system stack. the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. figure 23. simple example of a sequence of interrupt requests with: - nested mode - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 main int 2 int0 int4 int3 int2 cpl is set to 7 cpl=2 cpl=7 ei inte rrupt 2 has priority level 2 inte rrupt 3 has priority level 3 inte rrupt 4 has priority level 4 inte rrupt 5 has priority level 5 main int 3 cpl=3 int 6 cpl=6 int5 int 0 cpl=0 int6 int2 inte rrupt 6 has priority level 6 inte rrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced next int 2 cpl=2 int 4 cpl=4 int 5 cpl=5 priority level of interrupt request 9
54/190 st90158 - interrupts arbitration modes (cont'd) end of interrupt routine the iret interrupt return instruction executes the following steps: the flag register is popped from system stack. if encsr is set, csr is popped from system stack. the pc high byte is popped from system stack. the pc low byte is popped from system stack. all unmasked interrupts are enabled by setting the cicr.ien bit. the priority level of the interrupted routine is popped from the special register (nicr) and copied into cpl. if encsr is reset, csr is used instead of isr, unless the program returns to another nested routine. the suspended routine thus resumes at the inter- rupted instruction. figure 23 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. figure 24 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level. figure 24. complex example of a sequence of interrupt requests with: - nested mode - ien set to 1 during the interrupt routine execution int 2 int 3 cpl=3 int 0 cpl=0 int6 6 5 4 3 2 1 0 7 main int 5 int 4 int0 int4 int3 int2 cpl is set to 7 cpl=5 cpl=4 cpl=2 cpl=7 ei interrupt 2 has priori ty level 2 interrupt 3 has priori ty level 3 interrupt 4 has priori ty level 4 interrupt 5 has priori ty level 5 int 2 int 4 cpl=2 cpl=4 int 5 cpl=5 main ei ei int 2 cpl=2 int 6 cpl=6 int5 int2 ei interrupt 6 has priori ty level 6 interrupt 0 has priori ty level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced just after ei priority level of interrupt request ei 9
55/190 st90158 - interrupts 4.6 external interrupts the standard st9 core contains 8 external inter- rupts sources grouped into four pairs. table 10. external interrupt channel grouping each source has a trigger control bit tea0,..ted1 (r242,eitr.0,..,7 page 0) to select triggering on the rising or falling edge of the external pin. if the trigger control bit is set to a1o, the corresponding pending bit ipa0,..,ipd1 (r243,eipr.0,..,7 page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the in- put pin. each source can be individually masked through the corresponding control bit ima0,..,imd1 (eimr.7,..,0). see figure 26. the priority level of the external interrupt sources can be programmed among the eight priority lev- els with the control register eiplr (r245). the pri- ority level of each pair is software defined using the bits prl2, prl1. for each pair, the even channel (a0,b0,c0,d0) of the group has the even priority level and the odd channel (a1,b1,c1,d1) has the odd (lower) priority level. figure 25. priority level examples n figure 25 shows an example of priority levels. figure 26 gives an overview of the external inter- rupt control bits and vectors. the source of the interrupt channel a0 can be selected between the external pin int0 (when ia0s = a1o, the reset value) or the on-chip timer/ watchdog peripheral (when ia0s = a0o). the source of the interrupt channel b0 can be selected between the external pin int2 (when (spen,bms)=(0,0)) or the on-chip spi peripher- al. the source of the interrupt channel c0 can be selected between the external pin int4 (when ints = a1o) or the on-chip standard timer. the source of the interrupt channel d0 can be selected between the external pin int6 (when int_sel = a0o) or the on-chip rccu. warning: when using channels shared by both external interrupts and peripherals, special care must be taken to configure their control registers for both peripherals and interrupts. table 11. multiplexed interrupt sources external interrupt channel int7 int6 intd1 intd0 int5 int4 intc1 intc0 int3 int2 intb1 intb0 int1 int0 inta1 inta0 channel internal interrupt source external interrupt source inta0 timer/watchdog int0 1 001001 pl2 d pl1d pl2 c pl1 c pl2b pl1b pl2a pl1a int.d1: int.c1: 001=1 int.d0: source priority priority source int.a0: 010=2 int.a1: 011=3 int.b1: 101=5 int.b0: 100=4 int.c0: 000=0 eiplr vr000151 0 100=4 101=5 9
56/190 st90158 - interrupts external interrupts (cont'd) figure 26. external interrupts control bits and vectors n n int a0 request vector priority level mask bit pending bit ima0 ipa0 v7 v6 v5 v4 0 000 a0o a1o ia0s watchdog/timer end of count int 0 pin int a1 request tea1 int 1 pin int b0 request int 2 pin int b1 request teb1 int 3 pin int c0 request int 4 pin int c1 request tec1 int 5 pin int d0 request ted0 int 6 pin int d1 request ted1 int 7 pin vector priority level mask bit pending bit ima1 ipa1 v7 v6 v5 v4 0 0 1 0 1 v7 v6 v5 v4 0 1 0 0 v7 v6 v5 v4 0 110 v7 v6 v5 v4 1 000 v7 v6 v5 v4 10 1 0 v7 v6 v5 v4 1 1 0 0 v7 v6 v5 v4 1 110 vecto r priority level vector priority level vecto r priority level vector priority level vector priority level vector priority level mask bit imb0 pending bit ipb0 pending bit ipb1 pending bit ipc0 pending bit ipc1 pending bit ipd0 pending bit ipd1 mask bit imb1 mask bit imc0 mask bit imc1 mask bit imd0 mask bit imd1 * shared channels, see warning * * spen,bm s spi interrupt ints std timer a1o a0o int_sel rccu a0o a1o tea0 tec0 teb0 * * a0,0o pl2a pl1a 1 pl2c pl1c 0 pl2b pl1b 0 pl2a pl1a 1 pl2b pl1b 0 pl2c pl1c 0 pl2d pl1d 1 pl2d pl1d 9
57/190 st90158 - interrupts 4.7 top level interrupt the top level interrupt channel can be assigned either to the external pin nmi or to the timer/ watchdog according to the status of the control bit eivr.tlis (r246.2, page 0). if this bit is high (the reset condition) the source is the external pin nmi. if it is low, the source is the timer/ watchdog end of count. when the source is the nmi external pin, the control bit eivr.tltev (r246.3; page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. when the selected event occurs, the cicr.tlip bit (r230.6) is set. depending on the mask situation, a top level interrupt request may be generated. two kinds of masks are available, a maskable mask and a non-maskable mask. the first mask is the cicr.tli bit (r230.5): it can be set or cleared to enable or disable respectively the top level inter- rupt request. if it is enabled, the global enable in- terrupt bit, cicr.ien (r230.4) must also be ena- bled in order to allow a top level request. the second mask nicr.tlnm (r247.7) is a set- only mask. once set, it enables the top level in- terrupt request independently of the value of cicr.ien and it cannot be cleared by the pro- gram. only the processor reset cycle can clear this bit. this does not prevent the user from ignor- ing some sources due to a change in tlis. the top level interrupt service routine cannot be interrupted by any other interrupt or dma request, in any arbitration mode, not even by a subsequent top level interrupt request. warning . the interrupt machine cycle of the top level interrupt does not clear the cicr.ien bit, and the corresponding iret does not set it. fur- thermore the tli never modifies the cpl bits and the nicr register. 4.8 on-chip peripheral interrupts the general structure of the peripheral interrupt unit is described here, however each on-chip pe- ripheral has its own specific interrupt unit contain- ing one or more interrupt channels, or dma chan- nels. please refer to the specific peripheral chap- ter for the description of its interrupt features and control registers. the on-chip peripheral interrupt channels provide the following control bits: interrupt pending bit (ip). set by hardware when the trigger event occurs. can be set/ cleared by software to generate/cancel pending interrupts and give the status for interrupt polling. interrupt mask bit (im). if im = a0o, no interrupt request is generated. if im =a1o an interrupt re- quest is generated whenever ip = a1o and cicr.ien = a1o. priority level (prl, 3 bits). these bits define the current priority level, prl=0: the highest pri- ority, prl=7: the lowest priority (the interrupt cannot be acknowledged) interrupt vector register (ivr, up to 7 bits). the ivr points to the vector table which itself contains the interrupt routine start address. figure 27. top level interrupt structure n n watchdog enable wden watchdog timer end of count nmi or tltev mux tlis tlip tlnm tli ien pending mask top level interrupt va00294 core reset request 9
58/190 st90158 - interrupts 4.9 interrupt response time the interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. one more cpuclk cycle is required when an interrupt is acknowledged. requests are sampled every 5 cpuclk cycles. if the interrupt request comes from an external pin, the trigger event must occur a minimum of one intclk cycle before the sampling time. when an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the cpu waits until the current instruction is termi- nated and then services the request. instruction execution can normally be aborted provided no write operation has been performed. for an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (div instruction), 53 clock cycles (divws and mul instructions) or 49 for other instructions. for a non-maskable top level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (div instruction), 49 clock cycles (divws and mul instructions) or 45 for other instructions. in order to guarantee edge detection, input signals must be kept low/high for a minimum of one intclk cycle. an interrupt machine cycle requires a basic 18 in- ternal clock cycles (cpuclk), to which must be added a further 2 clock cycles if the stack is in the register file. 2 more clock cycles must further be added if the csr is pushed (encsr =1). the interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. in wait for interrupt mode, a further cycle is re- quired as wake-up delay. 9
59/190 st90158 - interrupts 4.10 interrupt registers central interrupt control register (cicr) r230 - read/write register group: system reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable. this bit enables the 16-bit multifunction timer pe- ripheral. 0: mft disabled 1: mft enabled bit 6 = tlip : top level interrupt pending . this bit is set by hardware when top level inter- rupt (tli) trigger event occurs. it is cleared by hardware when a tli is acknowledged. it can also be set by software to implement a software tli. 0: no tli pending 1: tli pending bit 5 = tli : top level interrupt. this bit is set and cleared by software. 0: a top level interrupt is generared when tlip is set, only if tlnm=1 in the nicr register (inde- pendently of the value of the ien bit). 1: a top level interrupt request is generated when ien=1 and the tlip bit are set. bit 4 = ien : interrupt enable . this bit is cleared by the interrupt machine cycle (except for a tli). it is set by the iret instruction (except for a return from tli). it is set by the ei instruction. it is cleared by the di instruction. 0: maskable interrupts disabled 1: maskable interrupts enabled note: the ien bit can also be changed by soft- ware using any instruction that operates on regis- ter cicr, however in this case, take care to avoid spurious interrupts, since ien cannot be cleared in the middle of an interrupt arbitration. only modify the ien bit when interrupts are disabled or when no peripheral can generate interrupts. for exam- ple, if the state of ien is not known in advance, and its value must be restored from a previous push of cicr on the stack, use the sequence di; pop cicr to make sure that no interrupts are be- ing arbitrated when cicr is modified. bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software. 0: concurrent mode 1: nested mode bit 2:0 = cpl[2:0]: current priority level . these bits define the current priority level. cpl=0 is the highest priority. cpl=7 is the lowest priority. these bits may be modified directly by the interrupt hardware when nested interrupt mode is used. external interrupt trigger register (eitr) r242 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ted1 : intd1 trigger event bit 6 = ted0 : intd0 trigger event bit 5 = tec1 : intc1 trigger event bit 4 = tec0 : intc0 trigger event bit 3 = teb1 : intb1 trigger event bit 2 = teb0 : intb0 trigger event bit 1 = tea1 : inta1 trigger event bit 0 = tea0 : inta0 trigger event these bits are set and cleared by software. 0: select falling edge as interrupt trigger event 1: select rising edge as interrupt trigger event 70 gcen tlip tli ien iam cpl2 cpl1 cpl0 70 ted1 ted0 tec1 tec0 teb1 teb0 tea1 tea0 9
60/190 st90158 - interrupts interrupt registers (cont'd) external interrupt pending register (eipr) r243 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ipd1 : intd1 interrupt pending bit bit 6 = ipd0 : intd0 interrupt pending bit bit 5 = ipc1 : intc1 interrupt pending bit bit 4 = ipc0 : intc0 interrupt pending bit bit 3 = ipb1 : intb1 interrupt pending bit bit 2 = ipb0 : intb0 interrupt pending bit bit 1 = ipa1 : inta1 interrupt pending bit bit 0 = ipa0 : inta0 interrupt pending bit these bits are set by hardware on occurrence of a trigger event (as specified in the eitr register) and are cleared by hardware on interrupt acknowl- edge. they can also be set by software to imple- ment a software interrupt. 0: no interrupt pending 1: interrupt pending external interrupt mask-bit register (eimr) r244 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = imd1 : intd1 interrupt mask bit 6 = imd0 : intd0 interrupt mask bit 5 = imc1 : intc1 interrupt mask bit 4 = imc0 : intc0 interrupt mask bit 3 = imb1 : intb1 interrupt mask bit 2 = imb0 : intb0 interrupt mask bit 1 = ima1 : inta1 interrupt mask bit 0 = ima0 : inta0 interrupt mask these bits are set and cleared by software. 0: interrupt masked 1: interrupt not masked (an interrupt is generated if the ipxx and ien bits = 1) external interrupt priority level register (eiplr) r245 - read/write register page: 0 reset value: 1111 1111 (ffh ) bit 7:6 = pl2d, pl1d: intd0, d1 priority level. bit 5:4 = pl2c, pl1c : intc0, c1 priority level. bit 3:2 = pl2b, pl1b : intb0, b1 priority level. bit 1:0 = pl2a, pl1a : inta0, a1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for channels a0, b0, c0 and d0 and at 1 for channels a1, b1, c1 and d1. 70 ipd1 ipd0 ipc1 ipc0 ipb1 ipb0 ipa1 ipa0 70 imd1 imd0 imc1 imc0 imb1 imb0 ima1 ima0 70 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest) 9
61/190 st90158 - interrupts interrupt registers (cont'd) external interrupt vector register (eivr ) r246 - read/write register page: 0 reset value: xxxx 0110b (x6h) bit 7:4 = v[7:4] : most significant nibble of external interrupt vector . these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:4] and the selected external interrupt channel, refer to figure 26. bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source bit 0 = ewen : external wait enable. this bit is set and cleared by software. 0: waitn pin disabled 1: waitn pin enabled (to stretch the external memory access cycle). note: for more details on wait mode refer to the section describing the waitn pin in the external memory chapter. nested interrupt control (nicr) r247 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = tlnm : top level not maskable . this bit is set by software and cleared only by a hardware reset. 0: top level interrupt maskable. a top level re- quest is generated if the ien, tli and tlip bits =1 1: top level interrupt not maskable. a top level request is generated if the tlip bit =1 bit 6:0 = hl[6:0] : hold level x these bits are set by hardware when, in nested mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the top level interrupt request). they are cleared by hardware at the iret execution when the routine at level x is recovered. 70 v7 v6 v5 v4 tltev tlis iaos ewen 70 tlnm hl6 hl5 hl4 hl3 hl2 hl1 hl0 9
62/190 st90158 - interrupts interrupt registers (cont'd) external memory register 2 (emr2) r246 - read/write register page: 21 reset value: 0000 1111 (0fh) bit 7, 5:0 = reserved, keep in reset state. refer to the external memory interface chapter. bit 6 = encsr : enable code segment register. this bit is set and cleared by software. it affects the st9 cpu behaviour whenever an interrupt re- quest is issued. 0: the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, isr is used instead of csr, and the in- terrupt stack frame is identical to that of the orig- inal st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster in- terrupt response time. the drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service rou- tines is thus limited to 64k bytes. 1: isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service routines to access the entire 4 mbytes of address space; the drawback is that the inter- rupt response time is slightly increased, be- cause of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. 70 0 encsr 0 0 1 1 1 1 9
63/190 st90158 - on-chip direct memory access (dma) 5 on-chip direct memory access (dma) 5.1 introduction the st9 includes on-chip direct memory access (dma) in order to provide high-speed data transfer between peripherals and memory or register file. multi-channel dma is fully supported by peripher- als having their own controller and dma chan- nel(s). each dma channel transfers data to or from contiguous locations in the register file, or in memory. the maximum number of bytes that can be transferred per transaction by each dma chan- nel is 222 with the register file, or 65536 with memory. the dma controller in the peripheral uses an indi- rect addressing mechanism to dma pointers and counter registers stored in the register file. this is the reason why the maximum number of trans- actions for the register file is 222, since two reg- isters are allocated for the pointer and counter. register pairs are used for memory pointers and counters in order to offer the full 65536 byte and count capability. 5.2 dma priority levels the 8 priority levels used for interrupts are also used to prioritize the dma requests, which are ar- bitrated in the same arbitration phase as interrupt requests. if the event occurrence requires a dma transaction, this will take place at the end of the current instruction execution. when an interrupt and a dma request occur simultaneously, on the same priority level, the dma request is serviced before the interrupt. an interrupt priority request must be strictly higher than the cpl value in order to be acknowledged, whereas, for a dma transaction request, it must be equal to or higher than the cpl value in order to be executed. thus only dma transaction requests can be acknowledged when the cpl=0. dma requests do not modify the cpl value, since the dma transaction is not interruptable. figure 28. dma data transfer peripheral vr001834 data address counter transferred register file or memory register file register file start address counter value 0 df data group f peripheral paged registers 9
64/190 st90158 - on-chip direct memory access (dma) 5.3 dma transactions the purpose of an on-chip dma channel is to transfer a block of data between a peripheral and the register file, or memory. each dma transfer consists of three operations: a load from/to the peripheral data register to/ from a location of register file (or memory) ad- dressed through the dma address register (or register pair) a post-increment of the dma address register (or register pair) a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed. if the dma transaction is carried out between the peripheral and the register file (figure 29), one register is required to hold the dma address, and one to hold the dma transaction counter. these two registers must be located in the register file: the dma address register in the even address register, and the dma transaction counter in the next register (odd address). they are pointed to by the dma transaction counter pointer register (dcpr), located in the peripheral's paged regis- ters. in order to select a dma transaction with the register file, the control bit dcpr.rm (bit 0 of dcpr) must be set. if the transaction is made between the peripheral and memory , a register pair (16 bits) is required for the dma address and the dma transaction counter (figure 30). thus, two register pairs must be located in the register file. the dma transaction counter is pointed to by the dma transaction counter pointer register (dcpr), the dma address is pointed to by the dma address pointer register (dapr),both dcpr and dapr are located in the paged regis- ters of the peripheral. figure 29. dma between register file and peripheral idcr ivr dapr dcpr data paged registers registers system dma counter dma address ffh f0h e0h dfh efh memory 0000h data already transferred end of block interrupt service routine dma table dma transaction isr address 0100h vector table register file peripheral paged registers 9
65/190 st90158 - on-chip direct memory access (dma) dma transactions (cont'd) when selecting the dma transaction with memory, bit dcpr.rm (bit 0 of dcpr) must be cleared. to select between using the isr or the dmasr reg- ister to extend the address, (see memory manage- ment unit chapter), the control bit dapr.ps (bit 0 of dapr) must be cleared or set respectively. the dma transaction counter must be initialized with the number of transactions to perform and will be decremented after each transaction. the dma address must be initialized with the starting ad- dress of the dma table and is increased after each transaction. these two registers must be located between addresses 00h and dfh of the register file. once a dma channel is initialized, a transfer can start. the direction of the transfer is automatically defined by the type of peripheral and programming mode. once the dma table is completed (the transaction counter reaches 0 value), an interrupt request to the cpu is generated. when the interrupt pending (ip) bit is set by a hardware event (or by software), and the dma mask bit (dm) is set, a dma request is generated. if the priority level of the dma source is higher than, or equal to, the current priority level (cpl), the dma transfer is executed at the end of the cur- rent instruction. dma transfers read/write data from/to the location pointed to by the dma ad- dress register, the dma address register is incre- mented and the transaction counter register is decremented. when the contents of the transac- tion counter are decremented to zero, the dma mask bit (dm) is cleared and an interrupt request is generated, according to the interrupt mask bit (end of block interrupt). this end-of-block inter- rupt request is taken into account, depending on the prl value. warning . dma requests are not acknowledged if the top level interrupt service is in progress. figure 30. dma between memory and peripheral n idcr ivr dapr dcpr data paged registers registers system dma transaction counter dma address ffh f0h e0h dfh efh memory 0000h data already transferred end of block interrupt service routine dma table dma transaction isr address 0100h vector table register file peripheral paged registers 9
66/190 st90158 - on-chip direct memory access (dma) dma transactions (cont'd) 5.4 dma cycle time the interrupt and dma arbitration protocol func- tions completely asynchronously from instruction flow. requests are sampled every 5 cpuclk cycles. dma transactions are executed if their priority al- lows it. a dma transfer with the register file requires 8 cpuclk cycles. a dma transfer with memory requires 16 cpuclk cycles, plus any required wait states. 5.5 swap mode an extra feature which may be found on the dma channels of some peripherals (e.g. the multifunc- tion timer) is the swap mode. this feature allows transfer from two dma tables alternatively. all the dma descriptors in the register file are thus dou- bled. two dma transaction counters and two dma address pointers allow the definition of two fully in- dependent tables (they only have to belong to the same space, register file or memory). the dma transaction is programmed to start on one of the two tables (say table 0) and, at the end of the block, the dma controller automatically swaps to the other table (table 1) by pointing to the other dma descriptors. in this case, the dma mask (dm bit) control bit is not cleared, but the end of block interrupt request is generated to allow the optional updating of the first data table (table 0). until the swap mode is disabled, the dma control- ler will continue to swap between dma table 0 and dma table 1. n 9
67/190 st90158 - on-chip direct memory access (dma) 5.6 dma registers as each peripheral dma channel has its own spe- cific control registers, the following register list should be considered as a general example. the names and register bit allocations shown here may be different from those found in the peripheral chapters. dma counter pointer register (dcpr) read/write address set by peripheral reset value: undefined bit 7:1 = c[7:1] : dma transaction counter point- er. software should write the pointer to the dma transaction counter in these bits. bit 0 = rm : register file/memory selector. this bit is set and cleared by software. 0: dma transactions are with memory (see also dapr.dp) 1: dma transactions are with the register file generic external peripheral inter- rupt and dma control (idcr) read/write address set by peripheral reset value: undefined bit 5 = ip : interrupt pending . this bit is set by hardware when the trigger event occurs. it is cleared by hardware when the request is acknowledged. it can be set/cleared by software in order to generate/cancel a pending request. 0: no interrupt pending 1: interrupt pending bit 4 = dm : dma request mask . this bit is set and cleared by software. it is also cleared when the transaction counter reaches zero (unless swap mode is active). 0: no dma request is generated when ip is set. 1: dma request is generated when ip is set bit 3 = im : end of block interrupt mask . this bit is set and cleared by software. 0: no end of block interrupt request is generated when ip is set 1: end of block interrupt is generated when ip is set. dma requests depend on the dm bit value as shown in the table below. bit 2:0 = prl[2:0] : source priority level . these bits are set and cleared by software. refer to section 5.2 dma priority levels for a de- scription of priority levels. dma address pointer register (dapr) read/write address set by peripheral reset value: undefined bit 7:1 = a[7:1] : dma address register(s) pointer software should write the pointer to the dma ad- dress register(s) in these bits. bit 0 = ps : memory segment pointer selector : this bit is set and cleared by software. it is only meaningful if dapr.rm=0. 0: the isr register is used to extend the address of data transferred by dma (see mmu chapter). 1: the dmasr register is used to extend the ad- dress of data transferred by dma (see mmu chapter). 70 c7 c6 c5 c4 c3 c2 c1 rm 70 ip dm im prl2 prl1 prl0 dm im meaning 10 a dma request generated without end of block interrupt when ip=1 11 a dma request generated with end of block in- terrupt when ip=1 00 no end of block interrupt or dma request is generated when ip=1 01 an end of block interrupt is generated without associated dma request (not used) prl2 prl1 prl0 source priority level 0000h ighest 0011 0102 0113 1004 1015 1106 1117lo west 70 a7 a6 a5 a4 a3 a2 a1 ps 9
68/190 st90158 - reset and clock control unit (rccu) 6 reset and clock control unit (rccu) 6.1 introduction the reset and clock control unit (rccu) com- prises two distinct sections: the clock control unit, which generates and manages the internal clock signals. the reset/stop manager, which detects and flags hardware, software and watchdog gener- ated resets. on st9 devices where the external stop pin is available, this circuit also detects and manages the externally triggered stop mode, during which all oscillators are frozen in order to achieve the lowest possible power consumption. 6.2 clock control unit the clock control unit generates the internal clocks for the cpu core (cpuclk) and for the on- chip peripherals (intclk). the clock control unit may be driven by an external crystal circuit, con- nected to the oscin and oscout pins, or by an external pulse generator, connected to oscin (see figure 37 and figure 39). 6.2.1 clock control unit overview as shown in figure 31, a programmable divider can divide the clock1 input clock signal by two. the divide-by-two is recommended in order to en- sure a 50% duty cycle signal driving the pll mul- tiplier circuit. the resulting signal, clock2, is the reference input clock to the programmable phase locked loop frequency multiplier, which is capa- ble of multiplying the clock frequency by a factor of 6, 8, 10 or 14; the multiplied clock is then divided by a programmable divider, by a factor of 1 to 7. by this means, the st9 can operate with cheaper, medium frequency (3-5 mhz) crystals, while still providing a high frequency internal clock for maxi- mum system performance; the range of available multiplication and division factors allow a great number of operating clock frequencies to be de- rived from a single crystal frequency. for low power operation, especially in wait for in- terrupt mode, the clock multiplier unit may be turned off, whereupon the output clock signal may be programmed as clock2 divided by 16. for further power reduction, a low frequency external clock connected to the ck_af pin may be select- ed, whereupon the crystal controlled main oscilla- tor may be turned off. the internal system clock, intclk, is routed to all on-chip peripherals, as well as to the programma- ble clock prescaler unit which generates the clock for the cpu core (cpuclk). the clock prescaler is programmable and can slow the cpu clock by a factor of up to 8, allowing the programmer to reduce cpu processing speed, and thus power consumption, while maintaining a high speed clock to the peripherals. this is partic- ularly useful when little actual processing is being done by the cpu and the peripherals are doing most of the work. figure 31. clock control unit simplified block diagram quartz ck_af 1/16 1/2 oscillator source clock2 clock1 ck_af pll clock multiplier cpu clock prescaler to cpu core to peripherals cpuclk intclk unit /divider 1/4 to standard timer clock2/64 9
69/190 st90158 - reset and clock control unit (rccu) 6.3 clock management the various programmable features and operating modes of the ccu are handled by four registers: moder (mode register) this is a system register (r235, group e). the input clock divide-by-two and the cpu clock prescaler factors are handled by this register. clkctl (clock control register) this is a paged register (r240, page 55). the low power modes and the interpretation of the halt instruction are handled by this register. clk_flag (clock flag register) this is a paged register (r242, page 55). this register contains various status flags, as well as control bits for clock selection. pllconf (pll configuration register) this is a paged register (r246, page 55). the pll multiplication and division factors are programmed in this register. figure 32. clock control unit programming quartz pll ck_af 1/16 x 1/2 div2 ckaf_sel 1/n oscillator mx(1:0) 0 1 0 1 0 1 source ckaf_st csu_cksel 6/8/10/14 1 0 xt_div16 dx(2:0) clock2 clock1 (moder) (clk_flag) (clkctl) (pllconf) (clk_flag) ck_af intclk to peripherals and cpu clock prescaler xtstop (clk_flag) wait for interrupt and low power modes: lpowfi (clkctl) selects low power operation automatically on entering wfi mode. wfi_cksel (clkctl) selects the ck_af clock automatically, if present, on entering wfi mode. xtstop (clk_flag) automatically stops the xtal oscillator when the ck_af clock is present and selected. 9
70/190 st90158 - reset and clock control unit (rccu) clock management (cont'd) 6.3.1 pll clock multiplier programming the clock1 signal generated by the oscillator drives a programmable divide-by-two circuit. if the div2 control bit in moder is set (reset condi- tion), clock2, is equal to clock1 divided by two; if div2 is reset, clock2 is identical to clock1. since the input clock to the clock multi- plier circuit requires a 50% duty cycle for correct pll operation, the divide by two circuit should be enabled when a crystal oscillator is used, or when the external clock generator does not provide a 50% duty cycle. in practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the pll multiplier circuit. when the pll is active, it multiplies clock2 by 6, 8, 10 or 14, depending on the status of the mx0 -1 bits in pllconf. the multiplied clock is then di- vided by a factor in the range 1 to 7, determined by the status of the dx0-2 bits; when these bits are programmed to 111, the pll is switched off. following a reset phase, programming bits dx0-2 to a value different from 111 will turn the pll on. after allowing a stabilisation period for the pll, setting the csu_cksel bit in the clk_flag register selects the multiplier clock. the maximum frequency allowed for intclk is 24 mhz for 5v operation, and 16 mhz for 3v opera- tion. care is required, when programming the pll multiplier and divider factors, not to exceed the maximum permissible operating frequency for intclk, according to supply voltage. the st9 being a static machine, there is no lower limit for intclk. however, below 1mhz, a/d con- verter precision (if present) decreases. 6.3.2 cpu clock prescaling the system clock, intclk, which may be the out- put of the pll clock multiplier, clock2, clock2/ 16 or ck_af, drives a programmable prescaler which generates the basic time base, cpuclk, for the instruction executer of the st9 cpu core. this allows the user to slow down program execu- tion during non processor intensive routines, thus reducing power dissipation. the internal peripherals are not affected by the cpuclk prescaler and continue to operate at the full intclk frequency. this is particularly useful when little processing is being done and the pe- ripherals are doing most of the work. the prescaler divides the input clock by the value programmed in the control bits prs2,1,0 in the moder register. if the prescaler value is zero, no prescaling takes place, thus cpuclk has the same period and phase as intclk. if the value is different from 0, the prescaling is equal to the val- ue plus one, ranging thus from two (prs2,1,0 = 1) to eight (prs2,1,0 = 7). the clock generated is shown in figure 33, and it will be noted that the prescaling of the clock does not preserve the 50% duty cycle, since the high level is stretched to replace the missing cycles. this is analogous to the introduction of wait cycles for access to external memory. when external memory wait or bus request events occur, cpu- clk is stretched at the high level for the whole pe- riod required by the function. figure 33. cpu clock prescaling 6.3.3 peripheral clock the system clock, intclk, which may be the out- put of the pll clock multiplier, clock2, clock2/ 16 or ck_af, is also routed to all st9 on-chip pe- ripherals and acts as the central timebase for all timing functions. intclk cpuclk va00260 000 001 010 011 100 101 110 111 prs value 9
71/190 st90158 - reset and clock control unit (rccu) clock management (cont'd) 6.3.4 low power modes the user can select an automatic slowdown of clock frequency during wait for interrupt opera- tion, thus idling in low power mode while waiting for an interrupt. in wfi operation the clock to the cpu core (cpuclk) is stopped, thus suspending program execution, while the clock to the peripher- als (intclk) may be programmed as described in the following paragraphs. two examples of low power operation in wfi are illustrated in figure 34 and figure 35. if low power operation during wfi is disabled (lpowfi bit = 0 in the clkctl register), the cpu clk is stopped but intclk is unchanged. if low power operation during wait for interrupt is enabled (lpowfi bit = 1 in the clkctl register), as soon as the cpu executes the wfi instruction, the pll is turned off and the system clock will be forced to clock2 divided by 16, or to the external low frequency clock, ck_af, if this has been se- lected by setting wfi_cksel, and providing ckaf_st is set, thus indicating that the external clock is selected and actually present on the ck_af pin. if the external clock source is used, the crystal os- cillator may be stopped by setting the xtstop bit, providing that the ck_ak clock is present and se- lected, indicated by ckaf_st being set. the crys- tal oscillator will be stopped automatically on en- tering wfi if the wfi_cksel bit has been set. it should be noted that selecting a non-existent ck_af clock source is impossible, since such a selection requires that the auxiliary clock source be actually present and selected. in no event can a non-existent clock source be selected inadvert- ently. it is up to the user program to switch back to a fast- er clock on the occurrence of an interrupt, taking care to respect the oscillator and pll stabilisation delays, as appropriate. it should be noted that any of the low power modes may also be selected explicitly by the user pro- gram even when not in wait for interrupt mode, by setting the appropriate bits. 6.3.5 interrupt generation system clock selection modifies the clkctl and clk_flag registers. the clock control unit generates an external inter- rupt request when ck_af and clock2/16 are selected or deselected as system clock source, as well as when the system clock restarts after a hardware stop (when the stop mode feature is available on the specific device). this interrupt can be masked by resetting the int_sel bit in the clkctl register. note that this is the only case in the st9 where an an interrupt is generated with a high to low transition. table 12. summary of operating modes using main crystal controlled oscillator mode intclk cpuclk div2 prs0-2 csu_cksel mx1-0 dx2-0 lpowfi xt_div16 pll x by 14 xtal/2 x (14/d) intclk/n 1 n-1 1 1 0 d-1 x 1 pll x by 10 xtal/2 x (10/d) intclk/n 1 n-1 1 0 0 d-1 x 1 pll x by 8 xtal/2 x (8/d) intclk/n 1 n-1 1 1 1 d-1 x 1 pll x by 6 xtal/2 x (6/d) intclk/n 1 n-1 1 0 1 d-1 x 1 slow 1 xtal/2 intclk/n 1 n-1 x x 111 x 1 slow 2 xtal/32 intclk/n 1 n-1 x x x x 0 wait for interrupt if lpowfi=0, no changes occur on intclk, but cpuclk is stopped anyway. low power wait for interrupt xtal/32 stop 1 x x x x 1 1 reset xtal/2 intclk 1 0 0 00 111 0 1 example xtal=4.4 mhz 2.2*10/2 = 11mhz 11mhz 1 0 1 00 001 x 1 9
72/190 st90158 - reset and clock control unit (rccu) figure 34. example of low power mode programming in wfi using ck_af external clock user's program wfi instruction program flow intclk frequency interrupt pll multiply factor divider factor set wait for the pll to lock ck_af clock selected wait for interrupt no code is executed until interrupt serviced set to 10 to 1, and pll turned on an interrupt is requested low power mode enabled 2 mhz 20 mhz 2mhz 20 mhz ** t 2 = crystal oscillator start-up time *t 1 = pll lock-in time t 1 * t 2 ** f xtal = 4 mhz, v dd = 4.5 v min wait csu_cksel 1 pll is system clock source while ck_af is the system clock and the xtal restarts f ck_af the system clock switches to xtal in wfi state in wfi state user's program preselect xtal stopped when ck_af selected activated wait for the xtal pll is system clock source to stabilise wait for the pll to lock wfi_cksel 1 xtstop 1 lpowfi 1 wfi status dx2-0 000 mx(1:0) 00 reset state ck_af selected and xtal stopped automatically begin execution of user program resumes at full speed wait wait interrupt routine xtstop 0 ckaf_sel 0 csu_cksel 1 9
73/190 st90158 - reset and clock control unit (rccu) figure 35. example of low power mode programming in wfi using clock2/16 user's program wfi instruction program flow intclk frequency interrupt pll multiply factor divider factor set wait for the pll to lock wait for interrupt no code is executed until interrupt serviced set to 6 to 1, and pll turned on an interrupt is requested low power mode enabled 2mhz 12 mhz 2mhz 12 mhz *t 1 = pll lock-in time t 1 * t 1 * f xtal = 4 mhz, v dd = 2.7 v min wait csu_cksel 1 pll is system clock source pll switched on 125 khz in wfi state user's program activated pll is system clock source wait for the pll to lock wait lpowfi 1 wfi status interrupt routine csu_cksel 1 dx2-0 000 mx(1:0) 01 reset state clock2/16 selected and pll automatically begin clock2 selected stopped execution of user program resumes at full speed 9
74/190 st90158 - reset and clock control unit (rccu) 6.4 clock control registers mode register (moder) r235 - read/write system register reset value: 1110 0000 (e0h) *note : this register contains bits which relate to other functions; these are described in the chapter dealing with device architecture. only those bits relating to clock functions are described here. bit 5 = div2 : oscin divided by 2 . this bit controls the divide by 2 circuit which oper- ates on the oscin clock. 0: no division of the oscin clock 1: oscin clock is internally divided by 2 bit 4:2 = prs[2:0] : clock prescaling . these bits define the prescaler value used to pres- cale cpuclk from intclk. when these three bits are reset, the cpuclk is not prescaled, and is equal to intclk; in all other cases, the internal clock is prescaled by the value of these three bits plus one. clock control register (clkctl) r240 - read write register page: 55 reset value: 0000 0000 (00h) bit 7 = int_sel : interrupt selection . 0: the external interrupt channel input signal is se- lected (reset state) 1: select the internal rccu interrupt as the source of the interrupt request bit 4:6 = reserved for test purposes must be kept reset for normal operation. bit 3 = sresen : software reset enable. 0: the halt instruction turns off the quartz, the pll and the ccu 1: a reset is generated when halt is executed bit 2 = ckaf_sel : alternate function clock se- lect. 0: ck_af clock not selected 1: select ck_af clock note: to check if the selection has actually oc- curred, check that ckaf_st is set. if no clock is present on the ck_af pin, the selection will not occur. bit 1 = wfi_cksel : wfi clock select . this bit selects the clock used in low power wfi mode if lpowfi = 1. 0: intclk during wfi is clock2/16 1: intclk during wfi is ck_af, providing it is present. in effect this bit sets ckaf_sel in wfi mode warning : when the ck_af is selected as low power wfi clock but the xtal is not turned off (r242.4 = 0), after exiting from the wfi, ck_af will be still selected as system clock. in this case, reset the r240.2 bit to switch back to the xt. bit 0 = lpowfi : low power mode during wait for interrupt . 0: low power mode during wfi disabled. when wfi is executed, the cpuclk is stopped and intclk is unchanged 1: the st9 enters low power mode when the wfi instruction is executed. the clock during this state depends on wfi_cksel 70 - - div2 prs2 prs1 prs0 - - 70 int_s el --- sre- sen ckaf_s el wfi_cks el lpow fi 9
75/190 st90158 - reset and clock control unit (rccu) clock control registers (cont'd) clock flag register (clk_flag) r242 -read/write register page: 55 reset value: 0100 10x0 after a watchdog reset reset value: 0010 10x0 after a software reset reset value: 0000 10x0 after a power-on reset warning : if this register is accessed with a logi- cal instruction, such as and or or, some bits may not be set as expected. warning: if you select the ck_af as system clock and turn off the oscillator (bits r240.2 and r242.4 at 1), and then switch back to the xt clock by resetting the r240.2 bit, you must wait for the oscillator to restart correctly (12ms). bit 7 = ex_stp : external stop flag this bit is set by hardware and cleared by soft- ware. 0: no external stop condition occurred 1: external stop condition occurred bit 6 = wdgres : watchdog reset flag. this bit is read only. 0: no watchdog reset occurred 1: watchdog reset occurred bit 5 = softres : software reset flag. this bit is read only. 0: no software reset occurred 1: software reset occurred (halt instruction) bit 4 = xtstop : external stop enable 0: external stop disabled 1: the xtal oscillator will be stopped as soon as the ck_af clock is present and selected, whether this is done explicitly by the user pro- gram, or as a result of wfi, if wfi_cksel has previously been set to select the ck_af clock during wfi. warning: when the program writes `1' to the xtstop bit, it will still be read as 0 and is only set when the ck_af clock is running (ckaf_st=1). take care, as any operation such as a subsequent and with ` 1' or an or with ` 0' to the xtstop bit will reset it and the oscillator will not be stopped even if ckaf_st is subsequently set. bit 3 = xt_div16 : clock/16 selection this bit is set and cleared by software. an interrupt is generated when the bit is toggled. 0: clock2/16 is selected and the pll is off 1: the input is clock2 (or the pll output de- pending on the value of csu_cksel) warning: after this bit is modified from 0 to 1, take care that the pll lock-in time has elapsed be- fore setting the csu_cksel bit. bit 2 = ckaf_st : (read only) if set, indicates that the alternate function clock has been selected. if no clock signal is present on the ck_af pin, the selection will not occur. if re- set, the pll clock, clock2 or clock2/16 is se- lected (depending on bit 0). bit 0 = csu_cksel : csu clock select this bit is set and cleared by software. it is also cleared by hardware when: bits dx[2:0] (pllconf) are set to 111; the quartz is stopped (by hardware or software); wfi is executed while the lpowfi bit is set; the xt_div16 bit (clk_flag) is forced to '0'. this prevents the pll, when not yet locked, from providing an irregular clock. furthermore, a `0' stored in this bit speeds up the pll's locking. 0: clock2 provides the system clock 1: the pll multiplier provides the system clock. note : setting the ckaf_sel bit overrides any other clock selection. resetting the xt_div16 bit 70 ex_ stp wdgre s sof- tres xt- stop xt_ div16 ckaf_ st - csu_ ck- sel 9
76/190 st90158 - reset and clock control unit (rccu) clock control registers (cont'd) pll configuration register (pllconf) r246 - read/write register page: 55 reset value: xx00 x111 bit 5:4 = mx[1:0] : pll multiplication factor . refer to table 13 for multiplier settings. warning: after these bits are modified, take care that the pll lock-in time has elapsed before setting the csu_cksel bit in the clk_flag reg- ister. bit 2:0 = dx[2:0] : pll output clock divider factor. refer to table 14 for divider settings. table 13. pll multiplication factors table 14. divider configuration figure 36. rccu general timing 70 - - mx1 mx0 - dx2 dx1 dx0 mx1 mx0 clock2 x 10 14 00 10 11 8 01 6 dx2 dx1 dx0 ck 0 0 0 pll clock/1 0 0 1 pll clock/2 0 1 0 pll clock/3 0 1 1 pll clock/4 1 0 0 pll clock/5 1 0 1 pll clock/6 1 1 0 pll clock/7 111 clock2 (pll off, reset state) pll multiplier clock2 intclk internal reset clock pll switched on by user 510 x clock1 pll lock-in time exit from reset pll selected by user boot rom execution user program execution reset phase filtered external reset <4 m s 20 m s vr02113b external reset 9
77/190 st90158 - reset and clock control unit (rccu) 6.5 oscillator characteristics the on-chip oscillator circuit uses an inverting gate circuit with tri-state output. notes : it is recommended to place the quartz or crystal as close as possible to the st9 to reduce the parasitic capacitance. at low temperature, frost and humidity might prevent a correct start-up of the oscillator. oscout must not be used to drive external cir- cuits. when the oscillator is stopped, oscout goes high impedance. in halt mode, set by means of the halt instruc- tion, the parallel resistor, r, is disconnected and the oscillator is disabled, forcing the internal clock, clock1, to a high level, and oscout to a high impedance state. to exit the halt condition and restart the oscilla- tor, an external reset pulse is required, having a a minimum duration of 12ms, as illustrated in fig- ure 41 it should be noted that, if the watchdog function is enabled, a halt instruction will not disable the os- cillator. this to avoid stopping the watchdog if a halt code is executed in error. when this occurs, the cpu will be reset when the watchdog times out or when an external reset is applied. table 15. oscillator transconductance figure 37. crystal oscillator table 16. crystal internal resistance( w ) (5v op.) table 17. crystal internal resistance( w ) (3v op.) legend : c l1 ,c l2 : maximum total capacitance on pins oscin and oscout (the value includes the external capaci- tance tied to the pin cl1 and cl2 plus the parasitic capac- itance of the board and of the device). note : the tables are relative to the fundamental quartz crystal only (not ceramic resonator). figure 38. internal oscillator schematic figure 39. external clock gm min typ max 5v operation ma/v 0.77 1.5 2.4 3v operation 0.42 0.73 1.47 oscin oscout c l1 c l2 st9 crystal clock 1m w *recommended for oscillator stability c 1 =c 2 freq. 56pf 47pf 33pf 22pf 5 mhz 110 120 210 340 4 mhz 150 200 330 510 3 mhz 270 350 560 850 c 1 =c 2 freq. 56pf 47pf 33pf 22pf 5 mhz 35 45 75 120 4 mhz 55 70 125 195 3 mhz 100 135 220 350 halt oscin oscout r in r out r oscin oscout clock input nc external clock st9 9
78/190 st90158 - reset and clock control unit (rccu) oscillator characteristics (cont'd) ceramic resonators murata electronics ceralock resonators have been tested with the st90158 at 3, 3.68, 4 and 5 mhz. some resonators have built-in capacitors (see table 18). the test circuit is shown in figure 40. figure 40. test circuit table 18 shows the recommended conditions at different frequencies. table 18. obtained results advantages of using ceramic resonators: cst and cstcc types have built-in loading ca- pacitors (those with values shown in parentheses ()). rp is always open in the previous table because there is no need for a parallel resistor with a reso- nator (it is needed only with a crystal). test conditions: the evaluation conditions are 2.7 to 5.5 v for the supply voltage and -40 to 85 c for the tempera- ture range. caution: the above circuit condition is for design reference only. recommended c1, c2 value depends on the cir- cuit board used. v dd c1 c2 oscin ceralock st90158 v2 v1 rp rd oscout v ss freq. (mhz) parts number c1 (pf) c2 (pf) rp (ohm) rd (ohm) 3 csa3.00mg 30 30 open 0 cst3.00mgw (30) (30) open 0 3.68 csa3.68mg 30 30 open 0 cst3.68mgw (30) (30) open 0 cstcc3.68mg (15) (15) open 0 4 csa4.00mg 30 30 open 0 cst4.00mgw (30) (30) open 0 cstcc4.00mg (15) (15) open 0 5 csa5.00mg 30 30 open 0 cst5.00mgw (30) (30) open 0 cstcc5.00mg (15) (15) open 0 9
79/190 st90158 - reset and clock control unit (rccu) 6.6 reset/stop manager the reset/stop manager resets the mcu when one of the three following events occurs: a hardware reset, initiated by a low level on the reset pin. a software reset, initiated by a halt instruction (when enabled). a watchdog end of count condition. the event which caused the last reset is flagged in the clk_flag register, by setting the sof- tres or the wdgres bits respectively; a hard- ware initiated reset will leave both these bits reset. the hardware reset overrides all other conditions and forces the st9 to the reset state. during re- set, the internal registers are set to their reset val- ues, where these are defined, and the i/o pins are set to the bidirectional weak pull-up mode. reset is asynchronous: as soon as the reset pin is driven low, a reset cycle is initiated. figure 41. oscillator start-up sequence and reset timing v dd max v dd min oscin intclk reset oscout pin 12ms (5v), 24ms (3v) vr02085a 9
80/190 st90158 - reset and clock control unit (rccu) reset/stop manager (cont'd) the on-chip timer/watchdog generates a reset condition if the watchdog mode is enabled (wcr.wden cleared, r252 page 0), and if the programmed period elapses without the specific code (aah, 55h) written to the appropriate register. the input pin reset is not driven low by the on- chip reset generated by the timer/watchdog. when the reset pin goes high again, 510 oscilla- tor clock cycles (clock1) are counted before ex- iting the reset state (+-1 clock1 period, depend- ing on the delay between the rising edge of the re- set pin and the first rising edge of clock1). sub- sequently a short boot routine is executed from the device internal boot rom, and control then passes to the user program. the boot routine sets the device characteristics and loads the correct values in the memory man- agement unit's pointer registers, so that these point to the physical memory areas as mapped in the specific device. the precise duration of this short boot routine varies from device to device, depending on the boot rom contents. at the end of the boot routine the program coun- ter will be set to the location specified in the reset vector located in the lowest two bytes of memory. 6.6.1 reset pin timing to improve the noise immunity of the device, the reset pin has a schmitt trigger input circuit with hysteresis. in addition, a filter will prevent an un- wanted reset in case of a single glitch of less than 50 ns on the reset pin. the device is certain to reset if a negative pulse of more than 20 m s is ap- plied. when the reset pin goes high again, a de- lay of up to 4 m s will elapse before the rccu de- tects this rising front. from this event on, 510 os- cillator clock cycles (clock1) are counted before exiting the reset state (+-1clock1 period de- pending on the delay between the positive edge the rccu detects and the first rising edge of clock1) if the st9 is a romless version, without on-chip program memory, the mermory interface ports are set to external memory mode (i.e alternate func- tion) and the memory accesses are made to exter- nal program memory with wait cycles insertion. figure 42. recommended signal to be applied on reset pin 6.7 external stop mode on st9 devices provided with an external stop pin, the reset/stop manager can also stop all os- cillators without resetting the device. to enter stop mode, the stop pin must be forced to a0o for a minimum of 4 system clock cycles; while the stop pin is kept at a0o, the mcu will re- main in stop mode and all context information will be preserved. during this condition the internal clock will be frozen in the high state. when the pin is forced back to a1o, the mcu resumes execution of the user program after a de- lay of 255 clock2 periods. on exiting from stop mode an interrupt is generat- ed and the ex_stp bit in clk_flag will be set, to indicate to the user program that the machine is exiting from stop mode. v reset v dd 0.7 v dd 0.3 v dd 20 m s minimum 9
81/190 st90158 - external memory interface (extmi) 7 external memory interface (extmi) 7.1 introduction the st9 external memory interface uses two reg- isters (emr1 and emr2) to configure external memory accesses. some interface signals are also affected by wcr - r252 page 0. if the two registers emr1 and emr2 are set to the proper values, the st9+ memory access cycle is similar to that of the original st9, with the only ex- ception that it is composed of just two system clock phases, named t1 and t2. during phase t1, the memory address is output on the as falling edge and is valid on the rising edge of as. port0 and port 1 maintain the address sta- ble until the following t1 phase. during phase t2, two forms of behavior are possi- ble. if the memory access is a read cycle, port 0 pins are released in high-impedance until the next t1 phase and the data signals are sampled by the st9 on the rising edge of ds. if the memory ac- cess is a write cycle, on the falling edge of ds, port 0 outputs data to be written in the external memory. those data signals are valid on the rising edge of ds and are maintained stable until the next address is output. note that ds is pulled low at the beginning of phase t2 only during an exter- nal memory access. figure 43. page 21 registers n dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu ext.mem page 21 mmu bit dprrem=0 sspl ssph uspl usph moder ppr rp1 rp0 flagr cicr p5 p4 p3 p2 p1 p0 dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 bit dprrem=1 sspl ssph uspl usph moder ppr rp1 rp0 flagr cicr p5 p4 p3 p2 p1 p0 dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers 9
82/190 st90158 - external memory interface (extmi) 7.2 external memory signals the access to external memory is made using the as, ds, ds2, rw, port 0, port1, and wait signals described below. refer to figure 45 7.2.1 as: address strobe as (output, active low, tristate) is active during the system clock high-level phase of each t1 memory cycle: an as rising edge indicates that memory address and read/write memory control signals are valid. as is released in high-imped- ance during the bus acknowledge cycle or under the processor control by setting the himp bit (moder.0, r235). depending on the device as is available as alternate function or as a dedicated pin. under reset, as is held high with an internal weak pull-up. the behavior of this signal is affected by the mc, asaf, eto, bsz, las[1:0] and uas[1:0] bits in the emr1 or emr2 registers. refer to the regis- ter description. 7.2.2 ds: data strobe ds (output,active low, tristate) is active during the internal clock high-level phase of each t2 memory cycle. during an external memory read cycle, the data on port 0 must be valid before the ds rising edge. during an external memory write cycle, the data on port 0 are output on the falling edge of ds and they are valid on the rising edge of ds. when the internal memory is accessed ds is kept high during the whole memory cycle. ds is released in high-impedance during bus acknowledge cycle or under processor control by setting the himp bit (moder.0, r235). under reset status, ds is held high with an internal weak pull-up. the behavior of this signal is affected by the mc, ds2en, and bsz bits in the emr1 register. refer to the register description. 7.2.3 ds2: data strobe 2 this additional data strobe pin (alternate function output, active low, tristate) is available on some st9 devices only. it allows two external memories to be connected to the st9, the upper memory block (a21=1 typically ram) and the lower memo- ry block (a21=0 typically rom) without any exter- nal logic. the selection between the upper and lower memory blocks depends on the a21 address pin value. the upper memory block is controlled by the ds pin while the lower memory block is controlled by the ds2 pin. when the internal memory is ad- dressed, ds2 is kept high during the whole mem- ory cycle. ds2 is released in high-impedance dur- ing bus acknowledge cycle or under processor control by setting the himp bit (moder.0, r235). ds2 is enabled via software as the alternate func- tion output of the associated i/o port bit (refer to specific st9 version to identify the specific port and pin). the behavior of this signal is affected by the ds2en, and bsz bits in the emr1 register. refer to the register description. 9
83/190 st90158 - external memory interface (extmi) external memory signals (cont'd) figure 44. effects of ds2en on the behavior of ds and ds2 n ds stretch t1 t2 t1 t2 no wait cycle 1 ds wait cycle system as (mc=0) ds2en=0 or (ds2en=1 and upper memory addressed): ds2en=1 and lower memory addressed: ds ds ds ds2 (mc=1, read) (mc=1, write) (mc=0) ds ds2 (mc=0) ds2 (mc=1, read) ds2 (mc=1, write) clock 9
84/190 st90158 - external memory interface (extmi) external memory signals (cont'd) figure 45. external memory read/write with a programmable wait n as stretch ds stretch address address address address data in data in data out data t1 t2 t1 t2 twa twd no wait cycle 1 as wait cycle 1 ds wait cycle always read write as (mc=0) ale (mc=1) p1 ds (mc=0) p0 multiplexed rw (mc=0) ds (mc=1) rw (mc=1) p0 multiplexed rw (mc=0) ds (mc=1) rw (mc=1) address address tavqv tavwh tavwl system clock 9
85/190 st90158 - external memory interface (extmi) external memory signals (cont'd) 7.2.4 rw: read/write rw (alternate function output, active low, tristate) identifies the type of memory cycle: rw=o1o identifies a memory read cycle, rw=o0o identifies a memory write cycle. it is defined at the beginning of each memory cycle and it remains stable until the following memory cycle. rw is re- leased in high-impedance during bus acknowl- edge cycle or under processor control by setting the himp bit (moder). rw is enabled via soft- ware as the alternate function output of the asso- ciated i/o port bit (refer to specific st9 device to identify the port and pin). under reset status, the associated bit of the port is set into bidirectional weak pull-up mode. the behavior of this signal is affected by the mc, eto and bsz bits in the emr1 register. refer to the register description. 7.2.5 breq, back: bus request, bus acknowledge note: these pins are available only on some st9 devices (see pin description). breq (alternate function input, active low) indi- cates to the st9 that a bus request has tried or is trying to gain control of the memory bus. once en- abled by setting the brqen bit (moder.1, r235), breq is sampled with the falling edge of the processor internal clock during phase t2. n n figure 46. external memory read/write sequence with external wait (wait pin) n t1 t2 t1 t2 always read write syst em as (mc=0) ale (mc=1) ds (mc=0) p0 multiplexed rw (mc=0) ds (mc=1) rw (mc=1) p0 multiplexed rw (mc=0) ds (mc=1) rw (mc=1) wai t p1 t1 t2 address add. add. add. d.out address d.out add. data out d.in d.in d.in address address address clock 9
86/190 st90158 - external memory interface (extmi) external memory signals (cont'd) whenever it is sampled low, the system clock is stretched and the external memory signals (as, ds, ds2, rw, p0 and p1) are released in high-im- pedance. the external memory interface pins are driven again by the st9 as soon as breq is sam- pled high. back (alternate function output, active low) indi- cates that the st9 has relinquished control of the memory bus in response to a bus request. breq is driven low when the external memory interface signals are released in high-impedance. at mcu reset, the bus request function is disabled. to enable it, configure the i/o port pins assigned to breq and back as alternate function and set the brqen bit in the moder register. 7.2.6 port 0 if port 0 (input/output, push-pull/open-drain/ weak pull-up) is used as a bit programmable par- allel i/o port, it has the same features as a regular port. when set as an alternate function, it is used as the external memory interface: it outputs the multiplexed address 8 lsb: a[7:0] /data bus d[7:0]. 7.2.7 port 1 if port 1 (input/output, push-pull/open-drain/ weak pull-up) is used as a bit programmable par- allel i/o port, it has the same features as a regular port. when set as an alternate function, it is used as the external memory interface to provide the 8 msb of the address a[15:8]. the behavior of the port 0 and 1 pins is affected by the bsz and eto bits in the emr1 register. refer to the register description. 7.2.8 wait: external memory wait wait (alternate function input, active low) indi- cates to the st9 that the external memory requires more time to complete the memory access cycle. if bit ewen (eivr) is set, the wait signal is sam- pled with the rising edge of the processor internal clock during phase t1 or t2 of every memory cy- cle. if the signal was sampled active, one more in- ternal clock cycle is added to the memory cycle. on the rising edge of the added internal clock cy- cle, wait is sampled again to continue or finish the memory cycle stretching. note that if wait is sampled active during phase t1 then as is stretched, while if wait is sampled active during phase t2 then ds is stretched. wait is enabled via software as the alternate function input of the associated i/o port bit (refer to specific st9 ver- sion to identify the specific port and pin). under reset status, the associated bit of the port is set to the bidirectional weak pull-up mode. refer to fig- ure 46 figure 47. application example ram 64 kbytes g e a0-a15 a15-a8 st9+ ds p1 q0-q7 p0 w rw d1-d8 as oe le q1-q8 a0-a7/d0-d7 latch 9
87/190 st90158 - external memory interface (extmi) 7.3 register description external memory register 1 (emr1) r245 - read/write register page: 21 reset value: 1000 0000 (80h) bit 7 = reserved. bit 6 = mc : mode control . 0: as, ds and rw pins keep the st9old mean- ing. 1: as pin becomes ale, address load enable (as inverted); thus memory adress, read/ write signals are valid whenever a falling edge of ale occurs. ds becomes oen, output enable: it keeps the st9old meaning during external read opera- tions, but is forced to a1o during external write operations. rw pin becomes wen, write enable: it follows the st9old ds meaning during external write operations, but is forced to a1o during external read operations. bit 5 = ds2en : data strobe 2 enable . 0: the ds2 pin is forced to a1o during the whole memory cycle. 1: if the lower memory block is addressed, the ds2 pin follows the st9old ds meaning (if mc=0) or it becomes oen (if mc=1). the ds pin is forced to 1 during the whole memory cy- cle. if the upper memory block is used, ds2 is forced to a1o during the whole memory cycle. the ds pin behaviour is not modified. refer to figure 44 bit 4 = asaf : address strobe as alternate func- tion. depending on the device, as can be either a ded- icated pin or a port alternate function. this bit is used only in the second case. 0: as alternate function disabled. 1: as alternate function enabled. bit 2 = eto : external toggle. 0: the external memory interface pins (as, ds, ds2, rw, port0, port1) toggle only if an access to external memory is performed. 1: when the internal memory protection is dis- abled (mask option available on some devices only), the above pins (except ds and ds2 which never toggle during internal memory accesses) toggle during both internal and external memory accesses. bit 1 = bsz : bus size. 0: all the i/o ports including the external memory interface pins use smaller, less noisy output buffers. this may limit the operation frequency of the device, unless the clock is slow enough or sufficient wait states are inserted. 1: all the i/o ports including the external memory interface pins (as, ds, ds2, r/w, port 0, 1) use larger, more noisy output buffers . bit 0 = reserved. warning : external memory must be correctly addressed before and after a write operation on the emr1 register. for example, if code is fetched from external memory using the st9old external memory interface configuration (mc=0), setting the mc bit will cause the device to behave unpre- dictably. 70 x mc ds2en asaf x eto bsz x 9
88/190 st90158 - external memory interface (extmi) register description (cont'd) external memory register 2 (emr2) r246 - read/write register page: 21 reset value: 0000 1111 (0fh) bit 7 = reserved. bit 6 = encsr : enable code segment register. this bit affects the st9 cpu behavior whenever an interrupt request is issued. 0: the cpu works in original st9 compatibility mode concerning stack frame during interrupts. for the duration of the interrupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. the drawback is that it is not possible for an interrupt service routine to per- form inter-segment calls or jumps: these instruc- tions would update the csr, which, in this case, is not used (isr is used instead). the code seg- ment size for all interrupt service routines is thus limited to 64k bytes. 1: if encsr is set, isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also re- store csr from the stack. this approach allows interrupt service routines to access the entire 4mbytes of address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. bit 5 = dprrem : data page registers remapping 0: the locations of the four mmu (memory man- agement unit) data page registers (dpr0, dpr1, dpr2 and dpr3) are in page 21. 1: the four mmu data page registers are swapped with that of the data registers of ports 0-3. refer to figure 43 bit 4 = memsel : memory selection. warning: must be set by the user when using the external memory interface (reset value is 0) . bit 3:2 = las[1:0] : lower memory address strobe stretch . these two bits contain the number of wait cycles (from 0 to 3) to add to the system clock to stretch as during external lower memory block accesses (msb of 22-bit internal address=0). the reset val- ue is 3. 70 - encsr dprrem mem sel las1 las0 uas1 uas0 9
89/190 st90158 - external memory interface (extmi) register description (cont'd) bit 1:0 = uas[1:0] : upper memory address strobe stretch . these two bits contain the number of wait cycles (from 0 to 3) to add to the system clock to stretch as during external upper memory block accesses (msb of 22-bit internal address=1). the reset val- ue is 3. warning : the emr2 register cannot be written during an interrupt service routine. wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 7 = reserved, forced by hardware to 0. bit 6 = wdgen : watchdog enable. for a description of this bit, refer to the timer/ watchdog chapter. warning : clearing this bit has the effect of set- ting the timer/watchdog to watchdog mode. un- less this is desired, it must be set to a1o. bit 5:3 = uds[2:0] : upper memory data strobe stretch. these bits contain the number of intclk cycles to be added automatically to ds for external upper memory block accesses. uds = 0 adds no addi- tional wait cycles. uds = 7 adds the maximum 7 intclk cycles (reset condition). bit 2:0 = lds[2:0] : lower memory data strobe stretch. these bits contain the number of intclk cycles to be added automatically to ds or ds2 (depend- ing on the ds2en bit of the emr1 register) for ex- ternal lower memory block accesses. lds = 0 adds no additional wait cycles, lds = 7 adds the maximum 7 intclk cycles (reset condition). note 1: the number of clock cycles added refers to intclk and not to cpuclk. note 2: the distinction between the upper memo- ry block and the lower memory block allows differ- ent wait cycles between the first 2 mbytes and the second 2 mbytes, and allows 2 different data strobe signals to be used to access 2 different memories. typically, the ram will be located above address 0x200000 and the rom below address 0x1fffff, with different access times. no extra hardware is required as ds is used to access the upper memory block and ds2 is used to access the lower memory block. warning: the reset value of the wait control register gives the maximum number of wait cy- cles for external memory. to get optimum perfor- mance from the st9, the user should write the uds[2:0] and lds[2:0] bits to 0, if the external ad- dressed memories are fast enough. 70 0 wdgen uds2 uds1 uds0 lds2 lds1 lds0 9
90/190 st90158 - i/o ports 8 i/o ports 8.1 introduction st9 devices feature flexible individually program- mable multifunctional input/output lines. refer to the pin description chapter for specific pin alloca- tions. these lines, which are logically grouped as 8-bit ports, can be individually programmed to pro- vide digital input/output and analog input, or to connect input/output signals to the on-chip periph- erals as alternate pin functions. all ports can be in- dividually configured as an input, bi-directional, output or alternate function. in addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. ports configured as open drain must never have voltage on the port pin exceeding v dd (refer to the electri- cal characteristics section). input buffers can be either ttl or cmos compatible. alternatively some input buffers can be permanently forced by hardware to operate as schmitt triggers. 8.2 specific port configurations refer to the pin description chapter for a list of the specific port styles and reset values. 8.3 port control registers each port is associated with a data register (pxdr) and three control registers (pxc0, pxc1, pxc2). these define the port configuration and al- low dynamic configuration changes during pro- gram execution. port data and control registers are mapped into the register file as shown in fig- ure 48. port data and control registers are treated just like any other general purpose register. there are no special instructions for port manipulation: any instruction that can address a register, can ad- dress the ports. data can be directly accessed in the port register, without passing through other memory or aaccumulatoro locations. figure 48. i/o register map group e group f page 2 group f page 3 group f page 43 system registers ffh reserved p7dr p9dr r255 feh p3c2 p7c2 p9c2 r254 fdh p3c1 p7c1 p9c1 r253 fch p3c0 p7c0 p9c0 r252 fbh reserved p6dr p8dr r251 fah p2c2 p6c2 p8c2 r250 f9h p2c1 p6c1 p8c1 r249 f8h p2c0 p6c0 p8c0 r248 f7h reserved reserved reserved r247 f6h p1c2 p5c2 r246 e5h p5dr r229 f5h p1c1 p5c1 r245 e4h p4dr r228 f4h p1c0 p5c0 r244 e3h p3dr r227 f3h reserved reserved r243 e2h p2dr r226 f2h p0c2 p4c2 r242 e1h p1dr r225 f1h p0c1 p4c1 r241 e0h p0dr r224 f0h p0c0 p4c0 r240 9
91/190 st90158 - i/o ports port control registers (cont'd) during reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output data register is set to ffh. this condition is also held after reset, except for ports 0 and 1 in rom- less devices, and can be redefined under software control. bidirectional ports without weak pull-ups are set in high impedance during reset. to ensure proper levels during reset, these ports must be externally connected to either v dd or v ss through external pull-up or pull-down resistors. other reset conditions may apply in specific st9 devices. 8.4 input/output bit configuration by programming the control bits pxc0.n and pxc1.n (see figure 49) it is possible to configure bit px.n as input, output, bidirectional or alternate function output, where x is the number of the i/o port, and n the bit within the port (n = 0 to 7). when programmed as input, it is possible to select the input level as ttl or cmos compatible by pro- gramming the relevant pxc2.n control bit, except where the schmitt trigger option is assigned to the pin. the output buffer can be programmed as push- pull or open-drain. a weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). each pin of an i/o port may assume software pro- grammable alternate functions (refer to the de- vice pin description and to section 8.5 alter- nate function architecture). to output signals from the st9 peripherals, the port must be configured as af out. on st9 devices with a/d converter(s), configure the ports used for analog inputs as af in. the basic structure of the bit px.n of a general pur- pose port px is shown in figure 50. independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal data bus to the output master latches. when the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the input latch) is transferred to the internal data bus. when px.n is programmed as an input : (see figure 51). the output buffer is forced tristate. the data present on the i/o pin is sampled into the input latch at the beginning of each instruc- tion execution. the data stored in the output master latch is copied into the output slave latch at the end of the execution of each instruction. thus, if bit px.n is reconfigured as an output or bidirectional, the data stored in the output slave latch will be re- flected on the i/o pin. 9
92/190 st90158 - i/o ports input/output bit configuration (cont'd) figure 49. control bits n table 19. port bit configuration table (n = 0, 1... 7; x = port number) (1) for a/d converter inputs. legend: x = port n = bit af = alternate function bid = bidirectional cmos= cmos standard input levels hi-z = high impedance in = input od = open drain out = output pp = push-pull ttl = ttl standard input levels wp = weak pull-up bit 7 bit n bit 0 pxc2 pxc27 pxc2n pxc20 pxc1 pxc17 pxc1n pxc10 pxc0 pxc07 pxc0n pxc00 general purpose i/o pins a/d pins pxc2n pxc1n pxc0n 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 pxn configuration bid bid out out in in af out af out af in pxn output type wp od od pp od hi-z hi-z pp od hi-z (1) pxn input type ttl (or schmitt trigger) ttl (or schmitt tr igger) ttl (or schmitt tri gger) ttl (or schmitt trigger) cmos (or schmitt tr igger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) analog input 9
93/190 st90158 - i/o ports input/output bit configuration (cont'd) figure 50. basic structure of an i/o port pin figure 51. input configuration n n figure 52. output configuration n output slave latch output master latch input latch internal data bus i/o pin push-pull tristate open drain weak pull-up from peripheral output output input bidirectional alternate function to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts alternate function input output bidirectional output master latch input latch output slave latch internal data bus i/o pin tristate to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts output master latch input latch output slave latch internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull to peripheral inputs and interrupts 9
94/190 st90158 - i/o ports input/output bit configuration (cont'd) when px.n is programmed as an output : (figure 52) the output buffer is turned on in an open-drain or push-pull configuration. the data stored in the output master latch is copied both into the input latch and into the out- put slave latch, driving the i/o pin, at the end of the execution of the instruction. when px.n is programmed as bidirectional : (figure 53) the output buffer is turned on in an open-drain or weak pull-up configuration (except when dis- abled in hardware). the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. the data stored in the output master latch is copied into the output slave latch, driving the i/ o pin, at the end of the execution of the instruc- tion. warning : due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithme- tic/logic and boolean instructions performed on a bidirectional port pin. these instructions use a read-modify-write se- quence, and the result written in the port register depends on the logical level present on the exter- nal pin. this may bring unwanted modifications to the port output register content. for example: port register content, 0fh external port value, 03h (bits 3 and 2 are externally forced to 0) a bset instruction on bit 7 will return: port register content, 83h external port value, 83h (bits 3 and 2 have been cleared). to avoid this situation, it is suggested that all oper- ations on a port, using at least one bit in bidirec- tional mode, are performed on a copy of the port register, then transferring the result with a load in- struction to the i/o port. when px.n is programmed as a digital alter- nate function output : (figure 54) the output buffer is turned on in an open-drain or push-pull configuration. the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. the signal from an on-chip function is allowed to load the output slave latch driving the i/o pin. signal timing is under control of the alternate function. if no alternate function is connected to px.n, the i/o pin is driven to a high level when in push-pull configuration, and to a high imped- ance state when in open drain configuration. figure 53. bidirectional configuration n n figure 54. alternate function configuration n n n n n n output master latch input latch output slave latch internal data bus i/o pin weak pull-up ttl (or schmitt trigger) open drain to peripheral inputs and interrupts input latch from internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull peripheral output to peripheral inputs and interrupts output slave latch 9
95/190 st90158 - i/o ports 8.5 alternate function architecture each i/o pin may be connected to three different types of internal signal: data bus input/output alternate function input alternate function output 8.5.1 pin declared as i/o a pin declared as i/o, is connected to the i/o buff- er. this pin may be an input, an output, or a bidi- rectional i/o, depending on the value stored in (pxc2, pxc1 and pxc0). 8.5.2 pin declared as an alternate input a single pin may be directly connected to several alternate inputs. in this case, the user must select the required input mode (with the pxc2, pxc1, pxc0 bits) and enable the selected alternate function in the control register of the peripheral. no specific port configuration is required to enable an alternate function input, since the input buffer is directly connected to each alternate function module on the shared pin. as more than one mod- ule can use the same input, it is up to the user soft- ware to enable the required module as necessary. parallel i/os remain operational even when using an alternate function input. the exception to this is when an i/o port bit is permanently assigned by hardware as an a/d bit. in this case , after soft- ware programming of the bit in af-od-ttl, the al- ternate function output is forced to logic level 1. the analog voltage level on the corresponding pin is directly input to the a/d. 8.5.3 pin declared as an alternate function output the user must select the af out configuration using the pxc2, pxc1, pxc0 bits. several alter- nate function outputs may drive a common pin. in such case, the alternate function output signals are logically anded before driving the common pin. the user must therefore enable the required alternate function output by software. warning : when a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input. 8.6 i/o status after wfi, halt and reset the status of the i/o ports during the wait for in- terrupt, halt and reset operational modes is shown in the following table. the external memory interface ports are shown separately. if only the in- ternal memory is being used and the ports are act- ing as i/o, the status is the same as shown for the other i/o ports. mode ext. mem - i/o ports i/o ports p0 p1, p2, p6 wfi high imped- ance or next address (de- pending on the last memory op- eration per- formed on port) next address not affected (clock outputs running) halt high imped- ance next address not affected (clock outputs stopped) reset alternate function push- pull (romless device) bidirectional weak pull-up (high im- pedance when disa- bled in hardware). 9
96/190 st90158 - timer/watchdog (wdt) 9 on-chip peripherals 9.1 timer/watchdog (wdt) important note: this chapter is a generic descrip- tion of the wdt peripheral. however depending on the st9 device, some or all of wdt interface signals described may not be connected to exter- nal pins. for the list of wdt pins present on the st9 device, refer to the device pinout description in the first section of the data sheet. 9.1.1 introduction the timer/watchdog (wdt) peripheral consists of a programmable 16-bit timer and an 8-bit prescal- er. it can be used, for example, to: generate periodic interrupts measure input signal pulse widths request an interrupt after a set number of events generate an output signal waveform act as a watchdog timer to monitor system in- tegrity the main wdt registers are: control register for the input, output and interrupt logic blocks (wdtcr) 16-bit counter register pair (wdthr, wdtlr) prescaler register (wdtpr) the hardware interface consists of up to five sig- nals: wdin external clock input wdout square wave or pwm signal output int0 external interrupt input nmi non-maskable interrupt input hw0sw1 hardware/software watchdog ena- ble. figure 55. timer/watchdog block diagram int0 1 input & clock control logic inen inmd1 inmd2 wdtpr 8-bit prescaler wdtrh , wdtrl 16-bit intclk/4 wdt outmd wrout output control logic interrupt control logic end of count reset top level interrupt reques t outen mux wdout 1 iaos tlis inta0 request nmi 1 wdgen hw0sw 1 1 wdin 1 mux downcou nter clock 1 pin not present on some st9 devices . 9
97/190 st90158 - timer/watchdog (wdt) timer/watchdog (cont'd) 9.1.2 functional description 9.1.2.1 external signals the hw0sw1 pin can be used to permanently en- able watchdog mode. refer to section 0.1.3.1. the wdin input pin can be used in one of four modes: event counter mode gated external input mode triggerable input mode retriggerable input mode the wdout output pin can be used to generate a square wave or a pulse width modulated signal. an interrupt, generated when the wdt is running as the 16-bit timer/counter, can be used as a top level interrupt or as an interrupt source connected to channel a0 of the external interrupt structure (replacing the int0 interrupt input). the counter can be driven either by an external clock, or internally by intclk divided by 4. 9.1.2.2 initialisation the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be loaded with initial val- ues before starting the timer/counter. if this is not done, counting will start with reset values. 9.1.2.3 start/stop the st_sp bit enables downcounting. when this bit is set, the timer will start at the beginning of the following instruction. resetting this bit stops the counter. if the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the timer registers (wdtrl, wdtrh). a new constant can be written in the wdtrh, wdtrl, wdtpr registers while the counter is running. the new value of the wdtrh, wdtrl registers will be loaded at the next end of count (eoc) condition while the new value of the wdtpr register will be effective immediately. end of count is when the counter is 0. when watchdog mode is enabled the state of the st_sp bit is irrelevant. 9.1.2.4 single/continuous mode the s_c bit allows selection of single or continu- ous mode.this mode bit can be written with the timer stopped or running. it is possible to toggle the s_c bit and start the counter with the same in- struction. single mode on reaching the end of count condition, the timer stops, reloads the constant, and resets the start/ stop bit. software can check the current status by reading this bit. to restart the timer, set the start/ stop bit. note: if the timer constant has been modified dur- ing the stop period, it is reloaded at start time. continuous mode on reaching the end of count condition, the coun- ter automatically reloads the constant and restarts. it is stopped only if the start/stop bit is reset. 9.1.2.5 input section if the timer/counter input is enabled (inen bit) it can count pulses input on the wdin pin. other- wise it counts the internal clock/4. for instance, when intclk = 20mhz, the end of count rate is: 3.35 seconds for maximum count (timer const. = ffffh, prescaler const. = ffh) 200 ns for minimum count (timer const. = 0000h, prescaler const. = 00h) the input pin can be used in one of four modes: event counter mode gated external input mode triggerable input mode retriggerable input mode the mode is configurable in the wdtcr. 9.1.2.6 event counter mode in this mode the timer is driven by the external clock applied to the input pin, thus operating as an event counter. the event is defined as a high to low transition of the input signal. spacing between trailing edges should be at least 8 intclk periods (or 400ns with intclk = 20mhz). counting starts at the next input event after the st_sp bit is set and stops when the st_sp bit is reset. 9
98/190 st90158 - timer/watchdog (wdt) timer/watchdog (cont'd) 9.1.2.7 gated input mode this mode can be used for pulse width measure- ment. the timer is clocked by intclk/4, and is started and stopped by means of the input pin and the st_sp bit. when the input pin is high, the tim- er counts. when it is low, counting stops. the maximum input pin frequency is equivalent to intclk/8. 9.1.2.8 triggerable input mode the timer (clocked internally by intclk/4) is started by the following sequence: setting the start-stop bit, followed by a high to low transition on the input pin. to stop the timer, reset the st_sp bit. 9.1.2.9 retriggerable input mode in this mode, the timer (clocked internally by intclk/4) is started by setting the st_sp bit. a high to low transition on the input pin causes counting to restart from the initial value. when the timer is stopped (st_sp bit reset), a high to low transition of the input pin has no effect. 9.1.2.10 timer/counter output modes output modes are selected by means of the out- en (output enable) and outmd (output mode) bits of the wdtcr register. no output mode (outen = a0o) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outen = a1o, outmd = a0o) the timer outputs a signal with a frequency equal to half the end of count repetition rate on the wd- out pin. with an intclk frequency of 20mhz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. pulse width modulated output mode (outen = a1o, outmd = a1o) the state of the wrout bit is transferred to the output pin (wdout) at the end of count, and is held until the next end of count condition. the user can thus generate pwm signals by modifying the status of the wrout pin between end of count events, based on software counters decre- mented by the timer watchdog interrupt. 9.1.3 watchdog timer operation this mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. the watchdog, when enabled, resets the mcu, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. the appli- cation program must be designed so as to correct- ly write to the wdtlr watchdog register at regu- lar intervals during all phases of normal operation. 9.1.3.1 hardware watchdog/software watchdog the hw0sw1 pin (when available) selects hard- ware watchdog or software watchdog. if hw0sw1 is held low: the watchdog is enabled by hardware immedi- ately after an external reset. (note: software re- set or watchdog reset have no effect on the watchdog enable status). the initial counter value (ffffh) cannot be mod- ified, however software can change the prescaler value on the fly. the wdgen bit has no effect. (note: it is not forced low). if hw0sw1 is held high, or is not present: the watchdog can be enabled by resetting the wdgen bit. 9.1.3.2 starting the watchdog in watchdog mode the timer is clocked by intclk/4. if the watchdog is software enabled, the time base must be written in the timer registers before enter- ing watchdog mode by resetting the wdgen bit. once reset, this bit cannot be changed by soft- ware. if the watchdog is hardware enabled, the time base is fixed by the reset value of the registers. resetting wdgen causes the counter to start, re- gardless of the value of the start-stop bit. in watchdog mode, only the prescaler constant may be modified. if the end of count condition is reached a system reset is generated. 9
99/190 st90158 - timer/watchdog (wdt) timer/watchdog (cont'd) 9.1.3.3 preventing watchdog system reset in order to prevent a system reset, the sequence aah, 55h must be written to wdtlr (watchdog timer low register). once 55h has been written, the timer reloads the constant and counting re- starts from the preset value. to reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the wdtlr register between the writing operations. the maximum allowed time between two reloads of the counter depends on the watchdog timeout period. 9.1.3.4 non-stop operation in watchdog mode, a halt instruction is regarded as illegal. execution of the halt instruction stops further execution by the cpu and interrupt ac- knowledgment, but does not stop intclk, cpu- clk or the watchdog timer, which will cause a system reset when the end of count condition is reached. furthermore, st_sp, s_c and the input mode selection bits are ignored. hence, regard- less of their status, the counter always runs in continuous mode, driven by the internal clock. the output mode should not be enabled, since in this context it is meaningless. figure 56. watchdog timer mode timer start counting write wdtrh,wdtrl wd en=0 write aah,55h intowdtrl reset software fail (e.g. infiniteloop) or peripheral fail v a00220 produce count reload value count g 9
100/190 st90158 - timer/watchdog (wdt) timer/watchdog (cont'd) 9.1.4 wdt interrupts the timer/watchdog issues an interrupt request at every end of count, when this feature is ena- bled. a pair of control bits, ia0s (eivr.1, interrupt a0 se- lection bit) and tlis (eivr.2, top level input se- lection bit) allow the selection of 2 interrupt sources (timer/watchdog end of count, or external pin) handled in two different ways, as a top level non maskable interrupt (software reset), or as a source for channel a0 of the external interrupt logic. a block diagram of the interrupt logic is given in figure 3. note: software traps can be generated by setting the appropriate interrupt pending bit. table 1 below, shows all the possible configura- tions of interrupt/reset sources which relate to the timer/watchdog. a reset caused by the watchdog will set bit 6, wdgres of r242 - page 55 (clock flag regis- ter). see section clock control regis- ters. figure 57. interrupt sources table 20. interrupt configuration legend: wdg = watchdog function sw trap = software trap note: if ia0s and tlis = 0 (enabling the watchdog eoc as interrupt source for both top level and inta0 interrupts), only the inta0 interrupt is taken into account. timer watc hdog reset wdgen (wcr.6) inta0 request ia0s (eivr .1) mux 0 1 int0 mux 0 1 top level interrup t request va00293 tlis (eivr.2) nmi control bits enabled sources operating mode wdgen ia0s tlis reset inta0 top level 0 0 0 0 0 0 1 1 0 1 0 1 wdg/ext reset wdg/ext reset wdg/ext reset wdg/ext reset sw trap sw trap ext pin ext pin sw trap ext pin sw trap ext pin watchdog watchdog watchdog watchdog 1 1 1 1 0 0 1 1 0 1 0 1 ext reset ext reset ext reset ext reset timer timer ext pin ext pin timer ext pin timer ext pin timer timer timer timer 9
101/190 st90158 - timer/watchdog (wdt) timer/watchdog (cont'd) 9.1.5 register description the timer/watchdog is associated with 4 registers mapped into group f, page 0 of the register file. wdthr : timer/watchdog high register wdtlr : timer/watchdog low register wdtpr : timer/watchdog prescaler register wdtcr : timer/watchdog control register three additional control bits are mapped in the fol- lowing registers on page 0: watchdog mode enable, (wcr.6) top level interrupt selection, (eivr.2) interrupt a0 channel selection, (eivr.1) note : the registers containing these bits also con- tain other functions. only the bits relevant to the operation of the timer/watchdog are shown here. counter register this 16 bit register (wdtlr, wdthr) is used to load the 16 bit counter value. the registers can be read or written aon the flyo. timer/watchdog high register (wdthr) r248 - read/write register page: 0 reset value: 1111 1111 (ffh) bit 7:0 = r[15:8] counter most significant bits . timer/watchdog low register (wdtlr) r249 - read/write register page: 0 reset value: 1111 1111b (ffh) bit 7:0 = r[7:0] counter least significant bits. timer/watchdog prescaler register (wdtpr) r250 - read/write register page: 0 reset value: 1111 1111 (ffh) bit 7:0 = pr[7:0] prescaler value. a programmable value from 1 (00h) to 256 (ffh). warning : in order to prevent incorrect operation of the timer/watchdog, the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be ini- tialised before starting the timer/watchdog. if this is not done, counting will start with the reset (un-in- itialised) values. watchdog timer control register (wdtcr) r251- read/write register page: 0 reset value: 0001 0010 (12h) bit 7 = st_sp : start/stop bit . this bit is set and cleared by software. 0: stop counting 1: start counting (see warning above) bit 6 = s_c : single/continuous . this bit is set and cleared by software. 0: continuous mode 1: single mode bit 5:4 = inmd[1:2] : input mode selection bits . these bits select the input mode: 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 70 st_sp s_c inmd1 inmd2 inen outmd wrout outen inmd1 inmd2 input mode 0 0 event counter 0 1 gated input (reset value) 1 0 triggerable input 1 1 retriggerable input 9
102/190 st90158 - timer/watchdog (wdt) timer/watchdog (cont'd) bit 3 = inen : input enable . this bit is set and cleared by software. 0: disable input section 1: enable input section bit 2 = outmd : output mode. this bit is set and cleared by software. 0: the output is toggled at every end of count 1: the value of the wrout bit is transferred to the output pin on every end of count if outen=1. bit 1 = wrout : write out . the status of this bit is transferred to the output pin when outmd is set; it is user definable to al- low pwm output (on reset wrout is set). bit 0 = outen : output enable bit . this bit is set and cleared by software. 0: disable output 1: enable output wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 6 = wdgen : watchdog enable (active low). resetting this bit via software enters the watch- dog mode. once reset, it cannot be set anymore by the user program. at system reset, the watch- dog mode is disabled. note: this bit is ignored if the hardware watchdog option is enabled by pin hw0sw1 (if available). external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source warning : to avoid spurious interrupt requests, the ia0s bit should be accessed only when the in- terrupt logic is disabled (i.e. after the di instruc- tion). it is also necessary to clear any possible in- terrupt pending requests on channel a0 before en- abling this interrupt channel. a delay instruction (e.g. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ia0s write instruction. other bits are described in the interrupt section. 70 x wdgen x x x x x x 70 x x x x x tlis ia0s x 9
103/190 st90158 - multifunction timer (mft) 9.2 multifunction timer (mft) 9.2.1 introduction the multifunction timer (mft) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic pwm generation and frequency measurement. the mft comprises a 16-bit up/down counter driven by an 8-bit programmable prescaler. the in- put clock may be intclk/3 or an external source. the timer features two 16-bit comparison regis- ters, and two 16-bit capture/load/reload regis- ters. two input pins and two alternate function out- put pins are available. several functional configurations are possible, for instance: 2 input captures on separate external lines, and 2 independent output compare functions with the counter in free-running mode, or 1 output com- pare at a fixed repetition rate. 1 input capture, 1 counter reload and 2 inde- pendent output compares. 2 alternate autoreloads and 2 independent out- put compares. 2 alternate captures on the same external line and 2 independent output compares at a fixed repetition rate. when two timers are present in an st9 device, a combined operating mode is available. an internal on-chip event signal can be used on some devices to control other on-chip peripherals. the two external inputs may be individually pro- grammed to detect any of the following: rising edges falling edges both rising and falling edges figure 58. mft simplified block diagram 9
104/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) the configuration of each input is programmed in the input control register. each of the two output pins can be driven from any of three possible sources: compare register 0 logic compare register 1 logic overflow/underflow logic each of these three sources can cause one of the following four actions, independently, on each of the two outputs: nop, set, reset, toggle in addition, an additional on-chip event signal can be generated by two of the three sources men- tioned above, i.e. over/underflow event and com- pare 0 event. this signal can be used internally to synchronise another on-chip peripheral. five maskable interrupt sources referring to an end of count condition, 2 input captures and 2 output compares, can generate 3 different interrupt re- quests (with hardware fixed priority), pointing to 3 interrupt routine vectors. two independent dma channels are available for rapid data transfer operations. each dma request (associated with a capture on the reg0r register, or with a compare on the cmp0r register) has pri- ority over an interrupt request generated by the same source. a swap mode is also available to allow high speed continuous transfers (see interrupt and dma chapter). figure 59. detailed block diagram 9
105/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.2 functional description the mft operating modes are selected by pro- gramming the timer control register (tcr) and the timer mode register (tmr). 9.2.2.1 trigger events a trigger event may be generated by software (by setting either the cp0 or the cp1 bits in the t_flagr register) or by an external source which may be programmed to respond to the rising edge, the falling edge or both by programming bits a0- a1 and b0-b1 in the t_icr register. this trigger event can be used to perform a capture or a load, depending on the timer mode (configured using the bits in table 24). an event on the txina input or setting the cp0 bit triggers a capture to, or a load from the reg0r register (except in bicapture mode, see section 9.2.2.11). an event on the txinb input or setting the cp1 bit triggers a capture to, or a load from the reg1r register. in addition, in the special case of oload from reg0r and monitor on reg1ro, it is possible to use the txinb input as a trigger for reg0r.o 9.2.2.2 one shot mode when the counter generates an overflow (in up- count mode), or an underflow (in down-count mode), that is to say when an end of count condi- tion is reached, the counter stops and no counter reload occurs. the counter may only be restarted by an external trigger on txina or b or a by soft- ware trigger on cp0 only. one shot mode is en- tered by setting the co bit in tmr. 9.2.2.3 continuous mode whenever the counter reaches an end of count condition, the counting sequence is automatically restarted and the counter is reloaded from reg0r (or from reg1r, when selected in biload mode). continuous mode is entered by resetting the c0 bit in tmr. 9.2.2.4 triggered and retriggered modes a triggered event may be generated by software (by setting either the cp0 or the cp1 bit in the t_flagr register), or by an external source which may be programmed to respond to the rising edge, the falling edge or both, by programming bits a0-a1 and b0-b1 in t_icr. in one shot and triggered mode, every trigger event arriving before an end of count, is masked. in one shot and retriggered mode, every trigger received while the counter is running, automatical- ly reloads the counter from reg0r. triggered/re- triggered mode is set by the ren bit in tmr. the txina input refers to reg0r and the txinb input refers to reg1r. warning . if the triggered mode is selected when the counter is in continuous mode, every trigger is disabled, it is not therefore possible to synchronise the counting cycle by hardware or software. 9.2.2.5 gated mode in this mode, counting takes place only when the external gate input is at a logic low level. the se- lection of txina or txinb as the gate input is made by programming the in0-in3 bits in t_icr. 9.2.2.6 capture mode the reg0r and reg1r registers may be inde- pendently set in capture mode by setting rm0 or rm1 in tmr, so that a capture of the current count value can be performed either on reg0r or on reg1r, initiated by software (by setting cp0 or cp1 in the t_flagr register) or by an event on the external input pins. warning . care should be taken when two soft- ware captures are to be performed on the same register. in this case, at least one instruction must be present between the first cp0/cp1 bit set and the subsequent cp0/cp1 bit reset instructions. 9.2.2.7 up/down mode the counter can count up or down depending on the state of the udc bit (up/down count) in tcr, or on the configuration of the external input pins, which have priority over udc (see input pin as- signment in t_icr). the udcs bit returns the counter up/down current status (see also the up/ down autodiscrimination mode in the input pin assignment section). 9
106/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.2.8 free running mode the timer counts continuously (in up or down mode) and the counter value simply overflows or underflows through ffffh or zero; there is no end of count condition as such, and no reloading takes place. this mode is automatically selected either in bicapture mode or by setting reg0r for a capture function (continuous mode must also be set). in autoclear mode, free running operation can be had, with the possibility of choosing a max- imum count value before overflow or underflow which is less than 2 16 (see autoclear mode). 9.2.2.9 monitor mode when the rm1 bit in tmr is reset, and the timer is not in bivalue mode, reg1r acts as a monitor, duplicating the current up or down counter con- tents, thus allowing the counter to be read aon the flyo. 9.2.2.10 autoclear mode a clear command forces the counter either to 0000h or to ffffh, depending on whether up- counting or downcounting is selected. the counter reset may be obtained either directly, through the ccl bit in tcr, or by entering the autoclear mode, through the ccp0 and ccmp0 bits in tcr. every capture performed on reg0r (if ccp0 is set), or every successful compare performed by cmp0r (if ccmp0 is set), clears the counter and reloads the prescaler. the clear on capture mode allows direct meas- urement of delta time between successive cap- tures on reg0r, while the clear on compare mode allows free running with the possibility of choosing a maximum count value before overflow or underflow which is less than 2 16 (see free run- ning mode). 9.2.2.11 bivalue mode depending on the value of the rm0 bit in tmr, the biload mode (rm0 reset) or the bicapture mode (rm0 set) can be selected as illustrated in figure 21 below: table 21. bivalue modes a) biload mode the biload mode is entered by selecting the bival- ue mode (bm set in tmr) and programming reg0r as a reload register (rm0 reset in tmr). at any end of count, counter reloading is per- formed alternately from reg0r and reg1r, (a low level for bm bit always sets reg0r as the cur- rent register, so that, after a low to high transition of bm bit, the first reload is always from reg0r). tmr bits timer operating modes rm0 rm1 bm 0 1 x x 1 1 biload mode bicapture mode 9
107/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) every software or external trigger event on reg0r performs a reload from reg0r resetting the biload cycle. in one shot mode (reload initiat- ed by software or by an external trigger), reloading is always from reg0r. b) bicapture mode the bicapture mode is entered by selecting the bi- value mode (the bm bit in tmr is set) and by pro- gramming reg0r as a capture register (the rm0 bit in tmr is set). every capture event, software simulated (by set- ting the cp0 flag) or coming directly from the txi- na input line, captures the current counter value alternately into reg0r and reg1r. when the bm bit is reset, reg0r is the current register, so that the first capture, after resetting the bm bit, is always into reg0r. 9.2.2.12 parallel mode when two timers are present on an st9 device, the parallel mode is entered when the eck bit in the tmr register of timer 1 is set. the timer 1 prescaler input is internally connected to the timer 0 prescaler output. timer 0 prescaler input is con- nected to the system clock line. by loading the prescaler register of timer 1 with the value 00h the two timers (timer 0 and timer 1) are driven by the same frequency in parallel mode. in this mode the clock frequency may be divided by a factor in the range from 1 to 2 16 . 9.2.2.13 autodiscriminator mode the phase difference sign of two overlapping puls- es (respectively on txinb and txina) generates a one step up/down count, so that the up/down con- trol and the counter clock are both external. the setting of the udc bit in the tcr register has no effect in this configuration. figure 60. parallel mode description prescaler 0 prescaler 1 timer 1 timer 0 intclk/ 3 note: timer 1 is not available on all devices. refer to (see note) block diagram and register map. the device 9
108/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.3 input pin assignment the two external inputs (txina and txinb) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by programming the two relevant bits (a0, a1 and b0, b1) for each input in the external input control register (t_icr). the 16 different functional modes of the two exter- nal inputs can be selected by programming bits in0 - in3 of the t_icr, as illustrated in figure 22 table 22. input pin function some choices relating to the external input pin as- signment are defined in conjunction with the rm0 and rm1 bits in tmr. for input pin assignment codes which use the in- put pins as trigger inputs (except for code 1010, trigger up:trigger down), the following conditions apply: a trigger signal on the txina input pin performs an u/d counter load if rm0 is reset, or an exter- nal capture if rm0 is set. a trigger signal on the txinb input pin always performs an external capture on reg1r. the txinb input pin is disabled when the bivalue mode is set. note : for proper operation of the external input pins, the following must be observed: the minimum external clock/trigger pulse width must not be less than the system clock (intclk) period if the input pin is programmed as rising or falling edge sensitive. the minimum external clock/trigger pulse width must not be less than the prescaler clock period (intclk/3) if the input pin is programmed as ris- ing and falling edge sensitive (valid also in auto discrimination mode). the minimum delay between two clock/trigger pulse active edges must be greater than the prescaler clock period (intclk/3), while the minimum delay between two consecutive clock/ trigger pulses must be greater than the system clock (intclk) period. the minimum gate pulse width must be at least twice the prescaler clock period (intclk/3). in autodiscrimination mode, the minimum delay between the input pin a pulse edge and the edge of the input pin b pulse, must be at least equal to the system clock (intclk) period. if a number, n, of external pulses must be count- ed using a compare register in external clock mode, then the compare register must be load- ed with the value [x +/- (n-1)], where x is the starting counter value and the sign is chosen de- pending on whether up or down count mode is selected. i c reg. in3-in0 bits txina input function txinb input function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used gate gate not used trigger gate trigger clock up up/down trigger up up/down autodiscr. trigger ext. clock trigger not used trigger not used trigger ext. clock not used ext. clock trigger clock down ext. clock trigger down not used autodiscr. ext. clock trigger gate 9
109/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.3.1 txina = i/o - txinb = i/o input pins a and b are not used by the timer. the counter clock is internally generated and the up/ down selection may be made only by software via the udc (software up/down) bit in the tcr regis- ter. 9.2.3.2 txina = i/o - txinb = trigger the signal applied to input pin b acts as a trigger signal on reg1r register. the prescaler clock is internally generated and the up/down selection may be made only by software via the udc (soft- ware up/down) bit in the tcr register. 9.2.3.3 txina = gate - txinb = i/o the signal applied to input pin a acts as a gate sig- nal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). the counter clock is internally generated and the up/down con- trol may be made only by software via the udc (software up/down) bit in the tcr register. 9.2.3.4 txina = gate - txinb = trigger both input pins a and b are connected to the timer, with the resulting effect of combining the actions relating to the previously described configurations. 9.2.3.5 txina = i/o - txinb = ext. clock the signal applied to input pin b is used as the ex- ternal clock for the prescaler. the up/down selec- tion may be made only by software via the udc (software up/down) bit in the tcr register. 9.2.3.6 txina = trigger - txinb = i/o the signal applied to input pin a acts as a trigger for reg0r, initiating the action for which the reg- ister was programmed (i.e. a reload or capture). the prescaler clock is internally generated and the up/down selection may be made only by software via the udc (software up/down) bit in the tcr register. (*) the timer is in one shot mode and regor in reload mode 9.2.3.7 txina = gate - txinb = ext. clock the signal applied to input pin b, gated by the sig- nal applied to input pin a, acts as external clock for the prescaler. the up/down control may be made only by software action through the udc bit in the tcr register. 9.2.3.8 txina = trigger - txinb = trigger the signal applied to input pin a (or b) acts as trig- ger signal for reg0r (or reg1r), initiating the action for which the register has been pro- grammed. the counter clock is internally generat- ed and the up/down selection may be made only by software via the udc (software up/down) bit in the tcr register. 9
110/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.3.9 txina = clock up - txinb = clock down the edge received on input pin a (or b) performs a one step up (or down) count, so that the counter clock and the up/down control are external. setting the udc bit in the tcr register has no effect in this configuration, and input pin b has priority on input pin a. 9.2.3.10 txina = up/down - txinb = ext clock an high (or low) level applied to input pin a sets the counter in the up (or down) count mode, while the signal applied to input pin b is used as clock for the prescaler. setting the udc bit in the tcr reg- ister has no effect in this configuration. 9.2.3.11 txina = trigger up - txinb = trigger down up/down control is performed through both input pins a and b. a edge on input pin a sets the up count mode, while a edge on input pin b (which has priority on input pin a) sets the down count mode. the counter clock is internally generated, and setting the udc bit in the tcr register has no effect in this configuration. 9.2.3.12 txina = up/down - txinb = i/o an high (or low) level of the signal applied on in- put pin a sets the counter in the up (or down) count mode. the counter clock is internally generated. setting the udc bit in the tcr register has no ef- fect in this configuration. 9
111/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.3.13 autodiscrimination mode the phase between two pulses (respectively on in- put pin b and input pin a) generates a one step up (or down) count, so that the up/down control and the counter clock are both external. thus, if the ris- ing edge of txinb arrives when txina is at a low level, the timer is incremented (no action if the ris- ing edge of txinb arrives when txina is at a high level). if the falling edge of txinb arrives when txina is at a low level, the timer is decremented (no action if the falling edge of txinb arrives when txina is at a high level). setting the udc bit in the tcr register has no ef- fect in this configuration. 9.2.3.14 txina = trigger - txinb = ext. clock the signal applied to input pin a acts as a trigger signal on reg0r, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin b is used as the clock for the prescaler. (*) the timer is in one shot mode and reg0r in reload mode 9.2.3.15 txina = ext. clock - txinb = trigger the signal applied to input pin b acts as a trigger, performing a capture on reg1r, while the signal applied to input pin a is used as the clock for the prescaler. 9.2.3.16 txina = trigger - txinb = gate the signal applied to input pin a acts as a trigger signal on reg0r, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin b acts as a gate signal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). 9
112/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.4 output pin assignment two external outputs are available when pro- grammed as alternate function outputs of the i/o pins. two registers output a control register (oacr) and output b control register (obcr) define the driver for the outputs and the actions to be per- formed. each of the two output pins can be driven from any of the three possible sources: compare register 0 event logic compare register 1 event logic overflow/underflow event logic. each of these three sources can cause one of the following four actions on any of the two outputs: nop set reset toggle furthermore an on chip event signal can be driv- en by two of the three sources: the over/under- flow event and compare 0 event by programming the cev bit of the oacr register and the oev bit of obcr register respectively. this signal can be used internally to synchronise another on-chip pe- ripheral. output waveforms depending on the programming of oacr and ob- cr, the following example waveforms can be gen- erated on txouta and txoutb pins. for a configuration where txouta is driven by the over/underflow (ouf) and the compare 0 event (cm0), and txoutb is driven by the over/under- flow and compare 1 event (cm1): oacr is programmed with txouta preset to a0o, ouf sets txouta, cm0 resets txouta and cm1 does not affect the output. obcr is programmed with txoutb preset to a0o, ouf sets txoutb, cm1 resets txoutb while cm0 does not affect the output. for a configuration where txouta is driven by the over/underflow, by compare 0 and by compare 1; txoutb is driven by both compare 0 and com- pare 1. oacr is programmed with txouta pre- set to a0o. ouf toggles output 0, as do cm0 and cm1. obcr is programmed with txoutb preset to a1o. ouf does not affect the output; cm0 resets txoutb and cm1 sets it. oacr = [101100x0] obcr = [111000x0] t0outa t0outb ouf comp1 ouf comp1 ouf comp0 ouf comp0 oacr = [010101x0] obcr = [100011x1] t0outa t0outb comp1 comp1 ouf ouf comp0 comp0 comp0 comp0 comp1 comp1 9
113/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) for a configuration where txouta is driven by the over/underflow and by compare 0, and txoutb is driven by the over/underflow and by compare 1. oacr is programmed with txouta preset to a0o. ouf sets txouta while cm0 resets it, and cm1 has no effect. obcr is programmed with tx- outb preset to a1o. ouf toggles txoutb, cm1 sets it and cm0 has no effect. for a configuration where txouta is driven by the over/underflow and by compare 0, and txoutb is driven by compare 0 and 1. oacr is pro- grammed with txouta preset to a0o. ouf sets txouta, cm0 resets it and cm1 has no effect. obcr is programmed with txoutb preset to a0o. ouf has no effect, cm0 sets txoutb and cm1 toggles it. output waveform samples in biload mode txouta is programmed to monitor the two time intervals, t1 and t2, of the biload mode, while tx- outb is independent of the over/underflow and is driven by the different values of compare 0 and compare 1. oacr is programmed with txouta preset to a0o. ouf toggles the output and cm0 and cm1 do not affect txouta. obcr is programmed with txoutb preset to a0o. ouf has no effect, while cm1 resets txoutb and cm0 sets it. depending on the cm1/cm0 values, three differ- ent sample waveforms have been drawn based on the above mentioned configuration of obcr. in the last case, with a different programmed value of obcr, only compare 0 drives txoutb, toggling the output. note (*) depending on the cmp1r/cmp0r values oacr = [101100x0] obcr = [000111x0] t0outa t0outb ouf ouf comp0 comp0 comp0 comp0 comp1 comp1 9
114/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.5 interrupt and dma 9.2.5.1 timer interrupt the timer has 5 different interrupt sources, be- longing to 3 independent groups, which are as- signed to the following interrupt vectors: table 23. timer interrupt structure the three least significant bits of the vector pointer address represent the relative priority assigned to each group, where 000 represents the highest pri- ority level. these relative priorities are fixed by hardware, according to the source which gener- ates the interrupt request. the 5 most significant bits represent the general priority and are pro- grammed by the user in the interrupt vector reg- ister (t_ivr). each source can be masked by a dedicated bit in the interrupt/dma mask register (idmr) of each timer, as well as by a global mask enable bit (id- mr.7) which masks all interrupts. if an interrupt request (cm0 or cp0) is present be- fore the corresponding pending bit is reset, an overrun condition occurs. this condition is flagged in two dedicated overrun bits, relating to the comp0 and capt0 sources, in the timer flag reg- ister (t_flagr). 9.2.5.2 timer dma two independent dma channels, associated with comp0 and capt0 respectively, allow dma trans- fers from register file or memory to the comp0 register, and from the capt0 register to register file or memory). if dma is enabled, the capt0 and comp0 interrupts are generated by the corre- sponding dma end of block event. their priority is set by hardware as follows: compare 0 destination e lower priority capture 0 source e higher priority the two dma request sources are independently maskable by the cp0d and cm0d dma mask bits in the idmr register. the two dma end of block interrupts are inde- pendently enabled by the cp0i and cm0i interrupt mask bits in the idmr register. 9.2.5.3 dma pointers the 6 programmable most significant bits of the dma counter pointer register (dcpr) and of the dma address pointer register (dapr) are com- mon to both channels (comp0 and capt0). the comp0 and capt0 address pointers are mapped as a pair in the register file, as are the comp0 and capt0 dma counter pair. in order to specify either the capt0 or the comp0 pointers, according to the channel being serviced, the timer resets address bit 1 for capt0 and sets it for comp0, when the d0 bit in the dcpr regis- ter is equal to zero (word address in register file). in this case (transfers between peripheral registers and memory), the pointers are split into two groups of adjacent address and counter pairs respectively. for peripheral register to register transfers (select- ed by programming a1o into bit 0 of the dcpr reg- ister), only one pair of pointers is required, and the pointers are mapped into one group of adjacent positions. the dma address pointer register (dapr) is not used in this case, but must be considered re- served. figure 61. pointer mapping for transfers between registers and memory interrupt source vector address comp 0 comp 1 xxxx x110 capt 0 capt 1 xxxx x100 overflow/underflow xxxx x000 register file address pointers comp0 16 bit addr pointer yyyyyy11(l) yyyyyy10(h) capt0 16 bit addr pointer yyyyyy01(l) yyyyyy00(h) dma counters comp0 dma 16 bit counter xxxxxx11(l) xxxxxx10(h) capt0 dma 16 bit counter xxxxxx01(l) xxxxxx00(h) 9
115/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) figure 62. pointer mapping for register to register transfers 9.2.5.4 dma transaction priorities each timer dma transaction is a 16-bit operation, therefore two bytes must be transferred sequen- tially, by means of two dma transfers. in order to speed up each word transfer, the second byte transfer is executed by automatically forcing the peripheral priority to the highest level (000), re- gardless of the previously set level. it is then re- stored to its original value after executing the transfer. thus, once a request is being serviced, its hardware priority is kept at the highest level re- gardless of the other timer internal sources, i.e. once a comp0 request is being serviced, it main- tains a higher priority, even if a capt0 request oc- curs between the two byte transfers. 9.2.5.5 dma swap mode after a complete data table transfer, the transac- tion counter is reset and an end of block (eob) condition occurs, the block transfer is completed. the end of block interrupt routine must at this point reload both address and counter pointers of the channel referred to by the end of block inter- rupt source, if the application requires a continu- ous high speed data flow. this procedure causes speed limitations because of the time required for the reload routine. the swap feature overcomes this drawback, al- lowing high speed continuous transfers. bit 2 of the dma counter pointer register (dcpr) and of the dma address pointer register (dapr), tog- gles after every end of block condition, alternately providing odd and even address (d2-d7) for the pair of pointers, thus pointing to an updated pair, after a block has been completely transferred. this allows the user to update or read the first block and to update the pointer values while the second is being transferred. these two toggle bits are soft- ware writable and readable, mapped in dcpr bit 2 for the cm0 channel, and in dapr bit 2 for the cp0 channel (though a dma event on a channel, in swap mode, modifies a field in dapr and dcpr common to both channels, the dapr/ dcpr content used in the transfer is always the bit related to the correct channel). swap mode can be enabled by the swen bit in the idcr register. warning : enabling swap mode affects both channels (cm0 and cp0). register file 8 bit counter xxxxxx11 compare 0 8 bit addr pointer xxxxxx10 8 bit counter xxxxxx01 capture 0 8 bit addr pointer xxxxxx00 9
116/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) 9.2.5.6 dma end of block interrupt routine an interrupt request is generated after each block transfer (eob) and its priority is the same as that assigned in the usual interrupt request, for the two channels. as a consequence, they will be serviced only when no dma request occurs, and will be subject to a possible ouf interrupt request, which has higher priority. the following is a typical eob procedure (with swap mode enabled): test toggle bit and jump. reload pointers (odd or even depending on tog- gle bit status). reset eob bit: this bit must be reset only after the old pair of pointers has been restored, so that, if a new eob condition occurs, the next pair of pointers is ready for swapping. verify the software protection condition (see section 9.2.5.7). read the corresponding overrun bit: this con- firms that no dma request has been lost in the meantime. reset the corresponding pending bit. reenable dma with the corresponding dma mask bit (must always be done after resetting the pending bit) return. warning : the eob bits are read/write only for test purposes. writing a logical a1o by software (when the swen bit is set) will cause a spurious interrupt request. these bits are normally only re- set by software. 9.2.5.7 dma software protection a second eob condition may occur before the first eob routine is completed, this would cause a not yet updated pointer pair to be addressed, with con- sequent overwriting of memory. to prevent these errors, a protection mechanism is provided, such that the attempted setting of the eob bit before it has been reset by software will cause the dma mask on that channel to be reset (dma disabled), thus blocking any further dma operation. as shown above, this mask bit should always be checked in each eob routine, to ensure that all dma transfers are properly served. 9.2.6 register description note: in the register description on the following pages, register and page numbers are given using the example of timer 0. on devices with more than one timer, refer to the device register map for the adresses and page numbers. 9
117/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) capture load 0 high register (reg0hr) r240 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (msb). capture load 0 low register (reg0lr) r241 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (lsb). capture load 1 high register (reg1hr) r242 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (msb). capture load 1 low register (reg1lr) r243 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (lsb). compare 0 high register (cmp0hr) r244 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the msb of the 16-bit value to be compared to the up/down counter content. compare 0 low register (cmp0lr) r245 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the lsb of the 16-bit value to be compared to the up/down counter content. compare 1 high register (cmp1hr) r246 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the msb of the 16-bit value to be compared to the up/down counter content. compare 1 low register (cmp1lr) r247 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the lsb of the 16-bit value to be compared to the up/down counter content. 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 9
118/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) timer control register (tcr) r248 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = cen : counter enable . this bit is anded with the global counter enable bit (gcen) in the cicr register (r230). the gcen bit is set after the reset cycle. 0: stop the counter and prescaler 1: start the counter and prescaler (without reload). note: even if cen=0, capture and loading will take place on a trigger event. bit 6 = ccp0 : clear on capture . 0: no effect 1: clear the counter and reload the prescaler on a reg0r or reg1r capture event bit 5 = ccmp0 : clear on compare . 0: no effect 1: clear the counter and reload the prescaler on a cmp0r compare event bit 4 = ccl : counter clear . this bit is reset by hardware after being set by software (this bit always returns a0o when read). 0: no effect 1: clear the counter without generating an inter- rupt request bit 3 = udc : up/down software selection . if the direction of the counter is not fixed by hard- ware (txina and/or txinb pins, see par. 10.3) it can be controlled by software using the udc bit. 0: down counting 1: up counting bit 2 = udcs : up/down count status . this bit is read only and indicates the direction of the counter. 0: down counting 1: up counting bit 1 = of0 : ovf/unf state . this bit is read only. 0: no overflow or underflow occurred 1: overflow or underflow occurred during a cap- ture on register 0 bit 0 = cs counter status . this bit is read only and indicates the status of the counter. 0: counter halted 1: counter running 70 cen ccp 0 ccmp 0 ccl udc udc s of0 cs 9
119/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) timer mode register (tmr) r249 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = oe1 : output 1 enable. 0: disable the output 1 (txoutb pin) and force it high. 1: enable the output 1 (txoutb pin) the relevant i/o bit must also be set to alternate function bit 6 = oe0 : output 0 enable. 0: disable the output 0 (txouta pin) and force it high 1: enable the output 0 (txouta pin). the relevant i/o bit must also be set to alternate function bit 5 = bm : bivalu e mode . this bit works together with the rm1 and rm0 bits to select the timer operating mode (see table 24). 0: disable bivalue mode 1: enable bivalue mode bit 4 = rm1 : reg1r mode . this bit works together with the bm and rm0 bits to select the timer operating mode. refer to table 24. note: this bit has no effect when the bivalue mode is enabled (bm=1). bit 3 = rm0 : reg0r mode . this bit works together with the bm and rm1 bits to select the timer operating mode. refer to table 24. table 24. timer operating modes bit 2 = eck timer clock control . 0: the prescaler clock source is selected depend- ing on the in0 - in3 bits in the t_icr register 1: enter parallel mode (for timer 1 and timer 3 only, no effect for timer 0 and 2). see section 9.2.2.12. bit 1 = ren : retrigger mode . 0: enable retriggerable mode 1: disable retriggerable mode bit 0 = co : continous/one shot mode . 0: continuous mode (with autoreload on end of count condition) 1: one shot mode 70 oe1 oe0 bm rm1 rm0 eck ren c0 tmr bits timer operating modes bm rm1 rm0 1 x 0 biload mode 1 x 1 bicapture mode 00 0 load from reg0r and monitor on reg1r 01 0 load from reg0r and capture on reg1r 00 1 capture on reg0r and monitor on reg1r 0 1 1 capture on reg0r and reg1r 9
120/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) external input control register (t_icr) r250 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7:4 = in[3:0] : input pin function. these bits are set and cleared by software. bit 3:2 = a[0:1] : txina pin event . these bits are set and cleared by software. bit 1:0 = b[0:1]: txinb pin event . these bits are set and cleared by software. prescaler register (prsr) r251 - read/write register page: 10 reset value: 0000 0000 (00h) this register holds the preset value for the 8-bit prescaler. the prsr content may be modified at any time, but it will be loaded into the prescaler at the following prescaler underflow, or as a conse- quence of a counter reload (either by software or upon external request). following a reset condition, the prescaler is au- tomatically loaded with 00h, so that the prescaler divides by 1 and the maximum counter clock is generated (oscin frequency divided by 6 when moder.5 = div2 bit is set). the binary value programmed in the prsr regis- ter is equal to the divider value minus one. for ex- ample, loading prsr with 24 causes the prescal- er to divide by 25. 70 in3 in2 in1 in0 a0 a1 b0 b1 in[3:0] bits txina pin function txinb input pin function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used gate gate not used trigger gate trigger clock up up/down trigger up up/down autodiscr. trigger ext. clock trigger not used trigger not used trigger ext. clock not used ext. clock trigger clock down ext. clock trigger down not used autodiscr. ext. clock trigger gate a0 a1 txina pin event 0 0 1 1 0 1 0 1 no operation falling edge sensitive rising edge sensitive rising and falling edges b0 b1 txinb pin event 0 0 1 1 0 1 0 1 no operation falling edge sensitive rising edge sensitive rising and falling edges 70 p7 p6 p5 p4 p3 p2 p1 p0 9
121/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) output a control register (oacr) r252 - read/write register page: 10 reset value: 0000 0000 note: whenever more than one event occurs si- multaneously, the action taken will be the result of anding the event bits xxe1-xxe0. bit 7:6 = c0e[0:1] : comp0 event bits . these bits are set and cleared by software. bit 5:4 = c1e[0:1]: comp1 event bits . these bits are set and cleared by software. bit 3:2 = oue[0:1] : ovf/unf event bits . these bits are set and cleared by software. note: whenever more than one event occurs si- multaneously, the action taken will be the result of anding the event xxe1-xxe0 bits. bit 1 = cev : on-chip event on cmp0r . this bit is set and cleared by software. 0: no action 1: a successful compare on cmp0r activates the on-chip event signal (a single pulse is generat- ed) bit 0 = op : txouta preset value . this bit is set and cleared by software and by hard- ware. the value of this bit is the preset value of the txouta pin. reading this bit returns the current state of the txouta pin (useful when it is selected in toggle mode). 70 c0e0 c0e1 c1e0 c1e1 oue0 oue1 cev 0p c0e0 c0e1 action on txouta pin on a suc- cessful compare of the cmp0r register 0 0 set 0 1 toggle 1 0 reset 1 1 nop c1e0 c1e1 action on txouta pin on a suc- cessful compare of the cmp1r reg- ister 0 0 set 0 1 toggle 1 0 reset 1 1 nop oue0 oue1 action on txouta pin on an over- flow or underflow on the u/d coun- ter 0 0 set 0 1 toggle 1 0 reset 1 1 nop 9
122/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) output b control register (obcr) r253 - read/write register page: 10 reset value: 0000 0000 (00h) note: whenever more than one event occurs si- multaneously, the action taken will be the result of anding the event bits xxe1-xxe0. bit 7:6 = c0e[0:1] : comp0 event bits . these bits are set and cleared by software. bit 5:4 = c1e[0:1]: comp1 event bits . these bits are set and cleared by software. bit 3:2 = oue[0:1] : ovf/unf event bits . these bits are set and cleared by software. bit 1 = oev : on-chip event on ovf/unf . this bit is set and cleared by software. 0: no action 1: an underflow/overflow activates the on-chip event signal (a single pulse is generated) bit 0 = op : txoutb preset value . this bit is set and cleared by software and by hard- ware. the value of this bit is the preset value of the txoutb pin. reading this bit returns the current state of the txoutb pin (useful when it is selected in toggle mode). 70 c0e0 c0e1 c1e0 c1e1 oue0 oue1 oev 0p c0e0 c0e1 action on txoutb pin on a suc- cessful compare of the cmp0r register 0 0 set 0 1 toggle 1 0 reset 1 1 nop c1e0 c1e1 action on txoutb pin on a suc- cessful compare of the cmp1r reg- ister 0 0 set 0 1 toggle 1 0 reset 1 1 nop oue0 oue1 action on txoutb pin on an over- flow or underflow on the u/d coun- ter 0 0 set 0 1 toggle 1 0 reset 1 1 nop 9
123/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) flag register (t_flagr) r254 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = cp0 : capture 0 flag. this bit is set by hardware after a capture on reg0r register. an interrupt is generated de- pending on the value of the gtien, cp0i bits in the idmr register and the a0 bit in the t_flagr register. the cp0 bit must be cleared by software. setting by software acts as a software load/cap- ture to/from the reg0r register. 0: no capture 0 event 1: capture 0 event occurred bit 6 = cp1 : capture 1 flag . this bit is set by hardware after a capture on reg1r register. an interrupt is generated de- pending on the value of the gtien, cp0i bits in the idmr register and the a0 bit in the t_flagr register. the cp1 bit must be cleared by software. setting by software acts as a capture event on the reg1r register, except when in bicapture mode. 0: no capture 1 event 1: capture 1 event occurred bit 5 = cm0 : compare 0 flag . this bit is set by hardware after a successful com- pare on the cmp0r register. an interrupt is gener- ated if the gtien and cm0i bits in the idmr reg- ister are set. the cm0 bit is cleared by software. 0: no compare 0 event 1: compare 0 event occurred bit 4 = cm1 : compare 1 flag. this bit is set after a successful compare on cmp1r register. an interrupt is generated if the gtien and cm1i bits in the idmr register are set. the cm1 bit is cleared by software. 0: no compare 1 event 1: compare 1 event occurred bit 3 = ouf : overflow/underflow . this bit is set by hardware after a counter over/ underflow condition. an interrupt is generated if gtien and oui=1 in the idmr register. the ouf bit is cleared by software. 0: no counter overflow/underflow 1: counter overflow/underflow bit 2 = ocp0 : overrun on capture 0. this bit is set by hardware when more than one int/dma requests occur before the cp0 flag is cleared by software or whenever a capture is sim- ulated by setting the cp0 flag by software. the ocp0 flag is cleared by software. 0: no capture 0 overrun 1: capture 0 overrun bit 1 = ocm0 : overrun on compare 0. this bit is set by hardware when more than one int/dma requests occur before the cm0 flag is cleared by software.the ocm0 flag is cleared by software. 0: no compare 0 overrun 1: compare 0 overrun bit 0 = a0 : capture interrupt function . this bit is set and cleared by software. 0: configure the capture interrupt as an or func- tion of reg0r/reg1r captures 1: configure the capture interrupt as an and func- tion of reg0r/reg1r captures 70 cp0 cp1 cm0 cm1 ouf ocp 0 ocm 0 a0 9
124/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) interrupt/dma mask register (idmr) r255 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = gtien : global timer interrupt enable . this bit is set and cleared by software. 0: disable all timer interrupts 1: enable all timer timer interrupts from enabled sources bit 6 = cp0d : capture 0 dma mask. this bit is set by software to enable a capt0 dma transfer and cleared by hardware at the end of the block transfer. 0: disable capture on reg0r dma 1: enable capture on reg0r dma bit 5 = cp0i : capture 0 interrupt mask . 0: disable capture on reg0r interrupt 1: enable capture on reg0r interrupt (or capt0 dma end of block interrupt if cp0d=1) bit 4 = cp1i : capture 1 interrupt mask . this bit is set and cleared by software. 0: disable capture on reg1r interrupt 1: enable capture on reg1r interrupt bit 3 = cm0d : compare 0 dma mask. this bit is set by software to enable a comp0 dma transfer and cleared by hardware at the end of the block transfer. 0: disable compare on cmp0r dma 1: enable compare on cmp0r dma bit 2 = cm0i : compare 0 interrupt mask . this bit is set and cleared by software. 0: disable compare on cmp0r interrupt 1: enable compare on cmp0r interrupt (or comp0 dma end of block interrupt if cm0d=1) bit 1 = cm1i : compare 1 interrupt mask . this bit is set and cleared by software. 0: disable compare on cmp1r interrupt 1: enable compare on cmp1r interrupt bit 0 = oui : overflow/underflow interrupt mask . this bit is set and cleared by software. 0: disable overflow/underflow interrupt 1: enable overflow/underflow interrupt dma counter pointer register (dcpr) r240 - read/write register page: 9 reset value: undefined bit 7:2 = dcp[7:2] : msbs of dma counter register address. these are the most significant bits of the dma counter register address programmable by soft- ware. the dcp2 bit may also be toggled by hard- ware if the timer dma section for the compare 0 channel is configured in swap mode. bit 1 = dma-srce : dma source selection. this bit is set and cleared by hardware. 0: dma source is a capture on reg0r register 1: dma destination is a compare on cmp0r reg- ister bit 0 = reg/mem : dma area selection . this bit is set and cleared by software. it selects the source and destination of the dma area 0: dma from/to memory 1: dma from/to register file 70 gt- ien cp0d cp0i cp1i cm0 d cm0i cm1i oui 70 dcp7 dcp6 dcp5 dcp4 dcp3 dcp2 dma srce reg/ mem 9
125/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) dma address pointer register (dapr) r241 - read/write register page: 9 reset value: undefined bit 7:2 = dap[7:2] : msb of dma address register location. these are the most significant bits of the dma ad- dress register location programmable by software. the dap2 bit may also be toggled by hardware if the timer dma section for the compare 0 channel is configured in swap mode. note: during a dma transfer with the register file, the dapr is not used; however, in swap mode, dapr(2) is used to point to the correct ta- ble. bit 1 = dma-srce : dma source selection. this bit is fixed by hardware. 0: dma source is a capture on reg0r register 1: dma destination is a compare on the cmp0r register bit 0 = prg/dat: dma memory selection . this bit is set and cleared by software. it is only meaningful if dcpr.reg/mem=0. 0: the isr register is used to extend the address of data transferred by dma (see mmu chapter). 1: the dmasr register is used to extend the ad- dress of data transferred by dma (see mmu chapter). interrupt vector register (t_ivr) r242 - read/write register page: 9 reset value: xxxx xxx0 this register is used as a vector, pointing to the 16-bit interrupt vectors in memory which contain the starting addresses of the three interrupt sub- routines managed by each timer. only one interrupt vector register is available for each timer, and it is able to manage three interrupt groups, because the 3 least significant bits are fixed by hardware depending on the group which generated the interrupt request. in order to determine which request generated the interrupt within a group, the t_flagr register can be used to check the relevant interrupt source. bit 7:3 = v[4:0]: msb of the vector address. these bits are user programmable and contain the five most significant bits of the timer interrupt vec- tor addresses in memory. in any case, an 8-bit ad- dress can be used to indicate the timer interrupt vector locations, because they are within the first 256 memory locations (see interrupt and dma chapters). bit 2:1 = w[1:0]: vector address bits. these bits are equivalent to bit 1 and bit 2 of the timer interrupt vector addresses in memory. they are fixed by hardware, depending on the group of sources which generated the interrupt request as follows:. bit 0 = this bit is forced by hardware to 0. 70 dap 7 dap 6 dap5 dap4 dap3 dap2 dma srce prg /dat reg/mem prg/dat dma source/destination 0 0 1 1 0 1 0 1 isr register used to address memory dmasr register used to address memory register file register file 70 v4 v3 v2 v1 v0 w1 w0 0 w1 w0 interrupt source 0 0 1 1 0 1 0 1 overflow/underflow even interrupt not available capture event interrupt compare event interrupt 9
126/190 st90158 - multifunction timer (mft) multifunction timer (cont'd) interrupt/dma control register (idcr) r243 - read/write register page: 9 reset value: 1100 0111 (c7h) bit 7 = cpe : capture 0 eob . this bit is set by hardware when the end of block condition is reached during a capture 0 dma op- eration with the swap mode enabled. when swap mode is disabled (swen bit = a0o), the cpe bit is forced to 1 by hardware. 0: no end of block condition 1: capture 0 end of block bit 6 = cme : compare 0 eob . this bit is set by hardware when the end of block condition is reached during a compare 0 dma op- eration with the swap mode enabled. when the swap mode is disabled (swen bit = a0o), the cme bit is forced to 1 by hardware. 0: no end of block condition 1: compare 0 end of block bit 5 = dcts : dma capture transfer source . this bit is set and cleared by software. it selects the source of the dma operation related to the channel associated with the capture 0. note: the i/o port source is available only on spe- cific devices. 0: reg0r register 1: i/o port. bit 4 = dctd : dma compare transfer destination . this bit is set and cleared by software. it selects the destination of the dma operation related to the channel associated with compare 0. note: the i/o port destination is available only on specific devices. 0: cmp0r register 1: i/o port bit 3 = swen : swap function enable . this bit is set and cleared by software. 0: disable swap mode 1: enable swap mode for both dma channels. bit 2:0 = pl[2:0]: interrupt/dma priority level . with these three bits it is possible to select the in- terrupt and dma priority level of each timer, as one of eight levels (see interrupt/dma chapter). i/o connection register (iocr) r248 - read/write register page: 9 reset value: 1111 1100 (fch) bit 7:2 = not used. bit 1 = sc1 : select connection odd. this bit is set and cleared by software. it selects if the txouta and txina pins for timer 1 and timer 3 are connected on-chip or not. 0: t1outa / t1ina and t3outa/ t3ina uncon- nected 1: t1outa connected internally to t1ina and t3outa connected internally to t3ina bit 0 = sc0 : select connection even. this bit is set and cleared by software. it selects if the txouta and txina pins for timer 0 and timer 2 are connected on-chip or not. 0: t0outa / t0ina and t2outa/ t2ina uncon- nected 1: t0outa connected internally to t0ina and t2outa connected internally to t2ina note: timer 1 and 2 are available only on some devices. refer to the device block diagram and register map. 70 cpe cme dcts dct d swe n pl2 pl1 pl0 70 sc1 sc0 9
127/190 st90158 - standard timer (stim) 9.3 standard timer (stim) important note: this chapter is a generic descrip- tion of the stim peripheral. depending on the st9 device, some or all of the interface signals de- scribed may not be connected to external pins. for the list of stim pins present on the particular st9 device, refer to the pinout description in the first section of the data sheet. 9.3.1 introduction the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes capa- bility. the standard timer uses an input pin (stin) and an output (stout) pin. these pins, when available, may be independent pins or connected as alternate functions of an i/o port bit. stin can be used in one of four programmable in- put modes: event counter, gated external input mode, triggerable input mode, retriggerable input mode. stout can be used to generate a square wave or pulse width modulated signal. the standard timer is composed of a 16-bit down counter with an 8-bit prescaler. the input clock to the prescaler can be driven either by an internal clock equal to intclk divided by 4, or by clock2 derived directly from the external oscilla- tor, divided by device dependent prescaler value, thus providing a stable time reference independ- ent from the pll programming or by an external clock connected to the stin pin. the standard timer end of count condition is able to generate an interrupt which is connected to one of the external interrupt channels. the end of count condition is defined as the counter underflow, whenever 00h is reached. figure 63. standard timer block diagram n stout 1 extern al input & clock control logic inen inmd1 inmd2 stp 8-bit prescaler sth,stl 16-bit stan dard timer clock outmd1 outmd2 outpu t control logic inter rupt control logic end of count ints interrupt request clock2/x stin 1 interrupt 1 downcounter (see note 2) note 2: depending on device, the source of the input & clock control logic block may be permanently connected either to stin or the rccu signal clock2/x. in devices without stin and clock2, the intclk/4 mux note 1: pin not present on all st9 devices . inen bit must be held at 0. 9
128/190 st90158 - standard timer (stim) standard timer (cont'd) 9.3.2 functional description 9.3.2.1 timer/counter control start-stop count. the st-sp bit (stc.7) is used in order to start and stop counting. an instruction which sets this bit will cause the standard timer to start counting at the beginning of the next instruc- tion. resetting this bit will stop the counter. if the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the standard timer registers during the stop peri- od. in this case, the new constant will be loaded as soon as counting is restarted. a new constant can be written in sth, stl, stp registers while the counter is running. the new value of the sth and stl registers will be loaded at the next end of count condition, while the new value of the stp register will be loaded immedi- ately. warning: in order to prevent incorrect counting of the standardtimer,the prescaler (stp) andcounter (stl, sth) registers must be initialised before the starting of the timer. if this is not done, counting will start with the reset values (sth=ffh, stl=ffh, stp=ffh). single/continuous mode. the s-c bit (stc.6) selects between the single or continuous mode. single mode: at the end of count, the standard timer stops, reloads the constant and resets the start/stop bit (the user programmer can inspect the timer current status by reading this bit). setting the start/stop bit will restart the counter. continuous mode: at the end of the count, the counter automatically reloads the constant and re- starts. itis only stoppedbyresettingthestart/stop bit. the s-c bit can be written either with the timer stopped or running. it is possible to toggle the s-c bit and start the standard timer with the same in- struction. 9.3.2.2 standard timer input modes (st9 devices with standard timer input stin) bits inmd2, inmd1 and inen are used to select the input modes. the input enable (inen) bit ena- bles the input mode selected by the inmd2 and inmd1 bits. if the input is disabled (inen=o0o), the values of inmd2 and inmd1 are not taken into ac- count. in this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by intclk/4 and transitions on the input pin have no effect. event counter mode (inmd1 = o0o, inmd2 = o0o) the standard timer is driven by the signal applied to the input pin (stin) which acts as an external clock. the unit works therefore as an event coun- ter. the event is a high to low transition on stin. spacing between trailing edges should be at least the period of intclk multiplied by 8 (i.e. the max- imum standard timer input frequency is 2.5 mhz with intclk = 20mhz). gated input mode (inmd1 = o0o, inmd2 = a1o) the timer uses the internal clock (intclk divided by 4) and starts and stops the timer according to the state of stin pin. when the status of the stin is high the standard timer count operation pro- ceeds, and when low, counting is stopped. triggerable input mode (inmd1= a1o,inmd2= a0o) the standard timer is started by: a) setting the start-stop bit, and b) a high to low (low trigger) transition on stin. in order to stop the standard timer in this mode, it is only necessary to reset the start-stop bit. retriggerable input mode (inmd1 = a1o, inmd2 = a1o) in this mode, when the standard timer is running (with internal clock), a high to low transition on stin causes the counting to start from the last constant loaded into the stl/sth and stp regis- ters. when the standard timer is stopped (st-sp bit equal to zero), a high to low transition on stin has no effect. 9.3.2.3 time base generator (st9 devices without standard timer input stin) for devices where stin is replaced by a connec- tion to clock2, the condition (inmd1 = a0o, inmd2 = a0o) will allow the standard timer to gen- erate a stable time base independent from the pll programming. 9
129/190 st90158 - standard timer (stim) standard timer (cont'd) 9.3.2.4 standard timer output modes output modes are selected using 2 bits of the stc register: outmd1 and outmd2. no output mode (outmd1 = a0o, outmd2 = a0o) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outmd1 = a0o, outmd2 = a1o) the standard timer toggles the state of the stout pin on every end of count condition. with intclk = 12mhz, this allows generation of a square wave with a period ranging from 666ns to 11.18 seconds. pwm output mode (outmd1 = a1o) the value of the outmd2 bit is transferred to the stout output pin at the end of count. this al- lows the user to generate pwm signals, by modi- fying the status of outmd2 between end of count events, based on software counters decremented on the standard timer interrupt. 9.3.3 interrupt selection the standard timer may generate an interrupt re- quest at every end of count. bit 2 of the stc register (ints) selects the inter- rupt source between the standard timer interrupt and the external interrupt pin. thus the standard timer interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. if ints is set to a1o, the standard timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every end of count. note: when enabling or disabling the standard timer interrupt (writing ints in the stc register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. to avoid this spurious interrupt request, the ints bit should be accessed only when the interrupt log- ic is disabled (i.e. after the di instruction). it is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. a delay instruction (i.e. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ints write instruction. 9.3.4 register mapping depending on the st9 device there may be up to 4 standard timers (refer to the block diagram in the first section of the data sheet). each standard timer has 4 registers mapped into page 11 in group f of the register file in the register description on the following page, register addresses refer to stim0 only. note: the four standard timers are not implement- ed on all st9 devices. refer to the block diagram of the device for the number of timers. std timer register register address stim0 sth0 r240 (f0h) stl0 r241 (f1h) stp0 r242 (f2h) stc0 r243 (f3h) stim1 sth1 r244 (f4h) stl1 r245 (f5h) stp1 r246 (f6h) stc1 r247 (f7h) stim2 sth2 r248 (f8h) stl2 r249 (f9h) stp2 r250 (fah) stc2 r251 (fbh) stim3 sth3 r252 (fch) stl3 r253 (fdh) stp3 r254 (feh) stc3 r255 (ffh) 9
130/190 st90158 - standard timer (stim) standard timer (cont'd) 9.3.5 register description counter high byte register (sth) r240 - read/write register page: 11 reset value: 1111 1111 (ffh) bit 7:0 = st.[15:8] : counter high-byte. counter low byte register (stl) r241 - read/write register page: 11 reset value: 1111 1111 (ffh) bit 7:0 = st.[7:0] : counter low byte. writing to the sth and stl registers allows the user to enter the standard timer constant, while reading it provides the counter's current value. thus it is possible to read the counter on-the-fly. standard timer prescaler register (stp) r242 - read/write register page: 11 reset value: 1111 1111 (ffh) bit 7:0 = stp.[7:0] : prescaler. the prescaler value for the standard timer is pro- grammed into this register. when reading the stp register, the returned value corresponds to the programmed data instead of the current data. 00h: no prescaler 01h: divide by 2 ffh: divide by 256 standard timer control register (stc) r243 - read/write register page: 11 reset value: 0001 0100 (14h) bit 7 = st-sp : start-stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting bit 6 = s-c : single-continuous mode select. this bit is set and cleared by software. 0: continuous mode 1: single mode bit 5:4 = inmd[1:2] : input mode selection. these bits select the input functions as shown in section 9.3.2.2, when enabled by inen. bit 3 = inen : input enable. this bit is set and cleared by software. if neither the stin pin nor the clock2 line are present, inen must be 0. 0: input section disabled 1: input section enabled bit 2 = ints : interrupt selection. 0: standard timer interrupt enabled 1: standard timer interrupt is disabled and the ex- ternal interrupt pin is enabled. bit 1:0 = outmd[1:2] : output mode selection. these bits select the output functions as described in section 9.3.2.4. 70 st.15 st.14 st.13 st.12 st.11 st.10 st.9 st.8 70 st.7 st.6 st.5 st.4 st.3 st.2 st.1 st.0 70 stp.7 stp.6 stp.5 stp.4 stp.3 stp.2 stp.1 stp.0 70 st- sp s-c inmd 1 inmd 2 inen ints outm d1 outm d2 inmd1 inmd2 mode 00 event counter mode 01 gated input mode 10 triggerable mode 11 retriggerable mode outmd1 outmd2 mode 00 no output mode 01 square wave output mode 1x pwm output mode 9
131/190 st90158 - serial peripheral interface (spi) 9.4 serial peripheral interface (spi) 9.4.1 introduction the serial peripheral interface (spi) is a general purpose on-chip shift register peripheral. it allows communication with external peripherals via an spi protocol bus. in addition, special operating modes allow re- duced software overhead when implementing i 2 c- bus and im-bus communication standards. the spi uses up to 3 pins: serial data in (sdi), serial data out (sdo) and synchronous serial clock (sck). additional i/o pins may act as device selects or im-bus address identifier signals. the main features are: n full duplex synchronous transfer if 3 i/o pins are used n master operation only n 4 programmable bit rates n programmable clock polarity and phase n busy flag n end of transmission interrupt n additional hardware to facilitate more complex protocols 9.4.2 device-specific options depending on the st9 variant and package type, the spi interface signals may not be connected to separate external pins. refer to the peripheral configuration chapter for the device pin-out. figure 64. block diagram n read buffer serial peripheral interface data register ( spidr ) polarity phase baud rate multiplexer st9 interrupt transmission end of spen bms arb busy cpol cpha spr1 spr0 data bus r254 intclk serial peripheral control register ( spicr ) r253 sdo sdi sck/int2 vr000347 10 int2 internal serial clock to mspi control logic i nt 2 intb0 * * common for transmit and receive 9
132/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) 9.4.3 functional description the spi, when enabled, receives input data from the internal data bus to the spi data register (spidr). a serial clock (sck) is generated by controlling through software two bits in the spi control register (spicr). the data is parallel loaded into the 8 bit shift register during a write cy- cle. this is shifted out serially via the sdo pin, msb first, to the slave device, which responds by sending its data to the master device via the sdi pin. this implies full duplex transmission if 3 i/o pins are used with both the data-out and data-in synchronized with the same clock signal, sck. thus the transmitted byte is replaced by the re- ceived byte, eliminating the need for separate atx emptyo and arx fullo status bits. when the shift register is loaded, data is parallel transferred to the read buffer and becomes availa- ble to the cpu during a subsequent read cycle. the spi requires three i/o port pins: sck serial clock signal sdo serial data out sdi serial data in an additional i/o port output bit may be used as a slave chip select signal. data and clock pins i c bus protocol are open-drain to allow arbitration and multiplexing. figure 65 below shows a typical spi network. figure 65. a typical spi network n 9.4.3.1 input signal description serial data in (sdi) data is transferred serially from a slave to a mas- ter on this line, most significant bit first. in an s- bus/i 2 c-bus configuration, the sdi line senses the value forced on the data line (by sdo or by an- other peripheral connected to the s-bus/i 2 c-bus). 9.4.3.2 output signal description serial data out (sdo) the sdo pin is configured as an output for the master device. this is obtained by programming the corresponding i/o pin as an output alternate function. data is transferred serially from a master to a slave on sdo, most significant bit first. the master device always allows data to be applied on the sdo line one half cycle before the clock edge, in order to latch the data for the slave device. the sdo pin is forced to high impedance when the spi is disabled. during an s-bus or i 2 c-bus protocol, when arbi- tration is lost, sdo is set to one (thus not driving the line, as sdo is configured as an open drain). master serial clock (sck) the master device uses sck to latch the incoming data on the sdi line. this pin is forced to a high im- pedance state when spi is disabled (spen, spicr.7 = a0o), in order to avoid clock contention from different masters in a multi-master system. the master device generates the sck clock from intclk. the sck clock is used to synchronize data transfer, both in to and out of the device, through its sdi and sdo pins. the sck clock type, and its relationship with data is controlled by the cpol (clock polarity) and cpha (clock phase) bits in the serial peripheral control regis- ter (spicr). this input is provided with a digital fil- ter which eliminates spikes lasting less than one intclk period. two bits, spr1 and spr0, in the serial peripheral control register (spicr), select the clock rate. four frequencies can be selected, two in the high frequency range (mostly used with the spi proto- col) and two in the medium frequency range (mostly used with more complex protocols). 9
133/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) figure 66. spi i/o pins n 9.4.4 interrupt structure the spi peripheral is associated with external in- terrupt channel b0 (pin int2). multiplexing be- tween the external pin and the spi internal source is controlled by the spen and bms bits, as shown in table 25. the two possible spi interrupt sources are: end of transmission (after each byte). s-bus/i 2 c-bus start or stop condition. care should be taken when toggling the spen and/or bms bits from the a0,0o condition. before changing the interrupt source from the external pin to the internal function, the b0 interrupt channel should be masked. eimr.2 (external interrupt mask register, bit 2, imbo) and eipr.2 (external interrupt pending register bit 2, imp0) should be a0o before changing the source. this sequence of events is to avoid the generating and reading of spurious interrupts. a delay instruction lasting at least 4 clock cycles (e.g. 2 nops) should be inserted between the spen toggle instruction and the interrupt pending bit reset instruction. the int2 input function is always mapped togeth- er with the sck input function, to allow start/stop bit detection when using s-bus/i 2 c-bus protocols. a start condition occurs when sdi goes from a1o to a0o and sck is a1o. the stop condition occurs when sdi goes from a0o to a1o and sck is a1o. for both stop and start conditions, spen = a0o and bms = a1o. table 25. interrupt configuration spi data bus port latch sdi sck int2 sdo sck sdo sdi int2 bit port latch bit port latch bit spen bms interrupt source 0 0 external channel int2 0 1 s-bus/i 2 c bus start or stop condition 1 x end of a byte transmission 9
134/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) 9.4.5 working with other protocols the spi peripheral offers the following facilities for operation with s-bus/i 2 c-bus and im-bus proto- cols: n interrupt request on start/stop detection n hardware clock synchronisation n arbitration lost flag with an automatic set of data line note that the i/o bit associated with the spi should be returned to a defined state as a normal i/o pin before changing the spi protocol. the following paragraphs provide information on how to manage these protocols. 9.4.6 i 2 c-bus interface the i 2 c-bus is a two-wire bidirectional data-bus, the two lines being sda (serial data) and scl (serial clock). both are open drain lines, to allow arbitration. as shown in figure 68, data is toggled with clock low. an i c bus start condition is the transition on sdi from 1 to 0 with the sck held high. in a stop condition, the sck is also high and the transition on sdi is from 0 to 1. during both of these conditions, if spen = 0 and bms = 1 then an interrupt request is performed. each transmission consists of nine clock pulses (scl line). the first 8 pulses transmit the byte (msb first), the ninth pulse is used by the receiver to acknowledge. figure 67. s-bus / i 2 c-bus peripheral compatibility without s-bus chip select 9
135/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) table 26. typical i 2 c-bus sequences figure 68. spi data and clock timing (for i2c protocol) n phase software hardware notes initialize spicr.cpol, cpha = 0, 0 spicr.spen = 0 spicr.bms = 1 sck pin set as af output sdi pin set as input set sdo port bit to 1 sck, sdo in hi-z scl, sda = 1, 1 set polarity and phase spi disable start/sto p interrupt enable start sdo pin set as output open drain set sdo port bit to 0 sda = 0, scl = 1 interrupt request start condition receiver start detection transmission spicr.spen = 1 sdo pin as alternate func- tion output load data into spidr scl = 0 start transmission interrupt request at end of byte transmission managed by interrupt rou- tine load ffh when receiv- ing end of transmission detection acknowledge spicr.spen = 0 poll sda line set sda line spicr.spen = 1 sck, sdo in hi-z scl, sda = 1 scl = 0 spi disable only if transmitting only if receiving only if transmitting stop sdo pin set as output open drain spicr.spen = 0 set sdo port bit to 1 sda = 1 interrupt request stop condition sda scl start condition 12 8 9 1st byte ack clock pulse for acknowledgement driven by software 12 89 driven by sw for acknowledgement clock pulse condition stop ack n byte th vr000188 9
136/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) the data on the sda line is sampled on the low to high transition of the scl line. spi working with an i2c-bus to use the spi with the i 2 c-bus protocol, the sck line is used as scl; the sdi and sdo lines, exter- nally wire-ored, are used as sda. all output pins must be configured as open drain (see figure 67). figure 26 illustrates the typical i 2 c-bus sequence, comprising 5 phases: initialization, start, trans- mission, acknowledge and stop. it should be not- ed that only the first 8 bits are handled by the spi peripheral; the acknowledge bit must be man- aged by software, by polling or forcing the scl and sdo lines via the corresponding i/o port bits. during the transmission phase, the following i 2 c- bus features are also supported by hardware. clock synchronization in a multimaster i 2 c-bus system, when several masters generate their own clock, synchronization is required. the first master which releases the scl line stops internal counting, restarting only when the scl line goes high (released by all the other masters). in this manner, devices using dif- ferent clock sources and different frequencies can be interfaced. arbitration lost when several masters are sending data on the sda line, the following takes place: if the transmit- ter sends a a1o and the sda line is forced low by another device, the arb flag (spicr.5) is set and the sdo buffer is disabled (arb is reset and the sdo buffer is enabled when spidr is written to again). when bms is set, the peripheral clock is supplied through the int2 line by the external clock line (scl). due to potential noise spikes (which must last longer than one intclk period to be detected), rx or tx may gain a clock pulse. referring to figure 69, if device st9-1 detects a noise spike and therefore gains a clock pulse, it will stop its transmission early and hold the clock line low, causing device st9-2 to freeze on the 7th bit. to exit and recover from this condition, the bms bit must be reset; this will cause the spi logic to be reset, thus aborting the current transmission. an end of transmission interrupt is generated fol- lowing this reset sequence. figure 69. spi arbitration n n internal serial clock bhs 0 1 st9-1 sck mspi logic control int 2 mspi control logic 0 1 bhs sck internal serial clock st9-2 int 2 1234567 st9-2-sck st9-1-sck 8 7 6 5 3 2 14 spike vr001410 9
137/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) 9.4.7 s-bus interface the s-bus is a three-wire bidirectional data-bus, possessing functional features similar to the i 2 c- bus. as opposed to the i 2 c-bus, the start/stop conditions are determined by encoding the infor- mation on 3 wires rather than on 2, as shown in figure 71. the additional line is referred as sen. spi working with s-bus the s-bus protocol uses the same pin configura- tion as the i 2 c-bus for generating the scl and sda lines. the additional sen line is managed through a standard st9 i/o port line, under soft- ware control (see figure 67). figure 70. mixed s-bus and i 2 c-bus system n figure 71. s-bus configuration n 12 3 4 56 start stop va00440 scl sda sen 9
138/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) 9.4.8 im-bus interface the im-bus features a bidirectional data line and a clock line; in addition, it requires an ident line to distinguish an address byte from a data byte (fig- ure 73). unlike the i 2 c-bus protocol, the im-bus protocol sends the least significant bit first; this re- quires a software routine which reverses the bit or- der before sending, and after receiving, a data byte. figure 72 shows the connections between an im-bus peripheral and an st9 spi. the sdo and sdi pins are connected to the bidirectional data pin of the peripheral device. the sdo alter- nate function is configured as open-drain (exter- nal 2.5k w pull-up resistors are required). with this type of configuration, data is sent to the peripheral by writing the data byte to the spidr register. to receive data from the peripheral, the user should write ffh to the spidr register, in or- der to generate the shift clock pulses. as the sdo line is set to the open-drain configuration, the in- coming data bits that are set to a1o do not affect the sdo/sdi line status (which defaults to a high level due to the ffh value in the transmit register), while incoming bits that are set to a0o pull the input line low. in software it is necessary to initialise the st9 spi by setting both cpol and cpha to a1o. by using a general purpose i/o as the ident line, and forcing it to a logical a0o when writing to the spidr regis- ter, an address is sent (or read). then, by setting this bit to a1o and writing to spidr, data is sent to the peripheral. when all the address and data pairs are sent, it is necessary to drive the ident line low and high to create a short pulse. this will generate the stop condition. figure 72. st9 and im-bus peripheral n figure 73. im bus timing v dd sck sdi sdo st9 mcu im-bus clock data ident im-bus slave device protocol portx vr001427 2.5 k 2x 1 23 45 6 clock line data line 1 2 4 3 5 6 msb vr000172 msb lsb lsb ident 9
139/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) 9.4.9 register description it is possible to have up to 3 independent spis in the same device (refer to the device block dia- gram). in this case they are named spi0 thru spi2. if the device has one spi converter it uses the register adresses of spi0. the register map is the following: note: in the register description on the following pages, register and page numbers are given using the example of spi0. spi data register (spidr) r253 - read/write register page: 0 reset value: undefined bit 7:0 = d[0:7] : spi data . this register contains the data transmitted and re- ceived by the spi. data is transmitted bit 7 first, and incoming data is received into bit 0. transmis- sion is started by writing to this register. note: spidr state remains undefined until the end of transmission of the first byte. spi control register (spicr) r254 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = spen : serial peripheral enable . 0: sck and sdo are kept tristate. 1: both alternate functions sck and sdo are ena- bled. note: furthermore, spen (together with the bms bit) affects the selection of the source for interrupt channel b0. transmission starts when data is writ- ten to the spidr register. bit 6 = bms : s-bus/i 2 c-bus mode selector . 0: perform a re-initialisation of the spi logic, thus allowing recovery procedures after a rx/tx fail- ure. 1: enable s-bus/i 2 c-bus arbitration, clock synchro- nization and start/ stop detection (spi used in an s-bus/i 2 c-bus protocol). note: when the bms bit is reset, it affects (togeth- er with the spen bit) the selection of the source for interrupt channel b0. bit 5 = arb : arbitration flag bit. this bit is set by hardware and can be reset by software. 0: s-bus/i 2 c-bus stop condition is detected. 1: arbitration lost by the spi in s-bus/i 2 c-bus mode. note: when arb is set automatically, the sdo pin is set to a high value until a write instruction on spidr is performed. bit 4 = busy : spi busy flag . this bit is set by hardware. it allows the user to monitor the spi status by polling its value. 0: no transmission in progress. 1: transmission in progress. bit 3 = cpol : transmission clock polarity . cpol controls the normal or steady state value of the clock when data is not being transferred. please refer to the following table and to figure 74 to see this bit action (together with the cpha bit). note: as the sck line is held in a high impedance state when the spi is disabled (spen = a0o), the sck pin must be connected to v ss or to v cc through a resistor, depending on the cpol state. polarity should be set during the initialisation rou- tine, in accordance with the setting of all peripher- als, and should not be changed during program execution. register spin page spidr r253 spi0 0 spicr r254 spi0 0 spidr1 r253 spi1 7 spicr1 r254 spi1 7 spidr2 r245 spi2 7 spicr2 r246 spi2 7 70 d7 d6 d5 d4 d3 d2 d1 d0 70 spen bms arb busy cpol cpha spr1 spr0 9
140/190 st90158 - serial peripheral interface (spi) serial peripheral interface (cont'd) bit 2 = cpha : transmission clock phase. cpha controls the relationship between the data on the sdi and sdo pins, and the clock signal on the sck pin. the cpha bit selects the clock edge used to capture data. it has its greatest impact on the first bit transmitted (msb), because it does (or does not) allow a clock transition before the first data capture edge. figure 74 shows the relation- ship between cpha, cpol and sck, and indi- cates active clock edges and strobe times. bit 1:0 = spr[1:0]: spi rate. these two bits select one (of four) baud rates, to be used as sck. figure 74. spi data and clock timing cpol cpha sck (in figure 74 ) 0 0 1 1 0 1 0 1 (a) (b) (c) (d) spr1 spr0 clock divider sck frequency (@ intclk = 12mhz) 0 0 1 1 0 1 0 1 8 16 128 256 1500khz 750khz 93.75khz 46.87khz (t = 0.67 m s) (t = 1.33 m s) (t = 10.66 m s) (t = 21.33 m s) 9
141/190 st90158 - serial communications interface (sci) 9.5 serial communications interface (sci) 9.5.1 introduction the serial communications interface (sci) offers full-duplex serial data exchange with a wide range of external equipment. the sci offers four operat- ing modes: asynchronous, asynchronous with synchronous clock, serial expansion and syn- chronous. the sci offers the following principal features: n full duplex synchronous and asynchronous operation. n transmit, receive, line status, and device address interrupt generation. n integral baud rate generator capable of dividing the input clock by any value from 2 to 2 16 -1 (16 bit word) and generating the internal 16x data sampling clock for asynchronous operation or the 1x clock for synchronous operation. n fully programmable serial interface: 5, 6, 7, or 8 bit word length. even, odd, or no parity generation and detec- tion. 0, 1, 1.5, 2, 2.5, 3 stop bit generation. complete status reporting capabilities. line break generation and detection. n programmable address indication bit (wake-up bit) and user invisible compare logic to support multiple microcomputer networking. optional character search function. n internal diagnostic capabilities: local loopback for communications link fault isolation. auto-echo for communications link fault isola- tion. n separate interrupt/dma channels for transmit and receive. n in addition, a synchronous mode supports: high speed communication possibility of hardware synchronization (rts/ dcd signals). programmable polarity and stand-by level for data sin/sout. programmable active edge and stand-by level for clocks clkout/rxcl. programmable active levels of rts/dcd sig- nals. full loop-back and auto-echo modes for da- ta, clocks and controls. figure 75. sci block diagram transmit buffer register register shift transmit register shift receiver function alternate register compare address register buffer receiver dma controller clock and baud rate generator st9 core bus sout txclk/clkout rxclk sin va00169a frame control and status dma controller rts dcd sds 9
142/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.2 functional description the sci offers four operating modes: asynchronous mode asynchronous mode with synchronous clock serial expansion mode synchronous mode asynchronous mode, asynchronous mode with synchronous clock and serial expansion mode output data with the same serial frame format. the differences lie in the data sampling clock rates (1x, 16x) and in the protocol used. figure 76. sci functional schematic note: some pins may not be available on some devices. refer to the device pinout description. divider by 16 1 0 1 0 divider by 16 cd cd the control signals marked with (*) are active only in synchronous mode (smen=1) polarity polarity txclk / clkout rx shift register tx buffer register tx shift register rtsen (*) enveloper aen (*) outsb (*) stand by polarity sout aen rx buffer register polarity polarity stand by polarity baud rate generator rxclk ocksb (*) lben (*) intclk xbrg aen (*) oclk xtclk dcden (*) dcd rts sin inpl (*) lben outpl (*) inpen (*) ockpl (*) xrx oclk vr02054 9
143/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.3 sci operating modes 9.5.3.1 asynchronous mode in this mode, data and clock can be asynchronous (the transmitter and receiver can use their own clocks to sample received data), each data bit is sampled 16 times per clock period. the baud rate clock should be set to the 16 mode and the frequency of the input clock (from an ex- ternal source or from the internal baud-rate gener- ator output) is set to suit. 9.5.3.2 asynchronous mode with synchronous clock in this mode, data and clock are synchronous, each data bit is sampled once per clock period. for transmit operation, a general purpose i/o port pin can be programmed to output the clkout signal from the baud rate generator. if the sci is provided with an external transmission clock source, there will be a skew equivalent to two intclk periods between clock and data. data will be transmitted on the falling edge of the transmit clock. received data will be latched into the sci on the rising edge of the receive clock. figure 77. sampling times in asynchronous format 012345 789101112131415 sdin rcvck rxd rxclk vr001409 legend: sin: rcvck: rxd: rxclk: serial data input line internal x16 receiver clock internal serial data input line internal receiver shift register sampling clock 9
144/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.3.3 serial expansion mode this mode is used to communicate with an exter- nal synchronous peripheral. the transmitter only provides the clock waveform during the period that data is being transmitted on the clkout pin (the data envelope). data is latched on the rising edge of this clock. whenever the sci is to receive data in serial port expansion mode, the clock must be supplied ex- ternally, and be synchronous with the transmitted data. the sci latches the incoming data on the ris- ing edge of the received clock, which is input on the rxclk pin. 9.5.3.4 synchronous mode this mode is used to access an external synchro- nous peripheral, dummy start/stop bits are not in- cluded in the data frame. polarity, stand-by level and active edges of i/o signals are fully and sepa- rately programmable for both inputs and outputs. it's necessary to set the smen bit of the synchro- nous input control register (sicr) to enable this mode and all the related extra features (otherwise disabled). the transmitter will provide the clock waveform only during the period when the data is being transmitted via the clkout pin, which can be en- abled by setting both the xtclk and oclk bits of the clock configuration register. whenever the sci is to receive data in synchronous mode, the clock waveform must be supplied externally via the rxclk pin and be synchronous with the data. for correct receiver operation, the xrx bit of the clock configuration register must be set. two external signals, request-to-send and data- carrier-detect (rts/dcd), can be enabled to syn- chronise the data exchange between two serial units. the rts output becomes active just before the first active edge of clkout and indicates to the target device that the mcu is about to send a synchronous frame; it returns to its stand-by state following the last active edge of clkout (msb transmitted). the dcd input can be considered as a gate that filters rxclk and informs the mcu that a trans- mitting device is transmitting a data frame. polarity of rts/dcd is individually programmable, as for clocks and data. the data word is programmable from 5 to 8 bits, as for the other modes; parity, address/9th, stop bits and break cannot be inserted into the transmitted frame. programming of the related bits of the sci control registers is irrelevant in synchronous mode: all the corresponding interrupt requests must, in any case, be masked in order to avoid in- correct operation during data reception. 9
145/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) figure 78. sci operating modes note: in all operating modes, the least significant bit is transmitted/received first. asynchronous mode asynchronous mode with synchronous clock serial expansion mode synchronous mode i/o clock start bit data parity stop bit 16 16 16 va00271 i/o clock start bit data parity stop bit va00272 i/o clock data va0273a start bit (dummy) stop bit (dummy) stand-by clock data vr02051 stand-by stand-by stand-by rts/dcd stand-by stand-by 9
146/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.4 serial frame format characters sent or received by the sci can have some or all of the features in the following format, depending on the operating mode: start : the start bit indicates the beginning of a data frame in asynchronous modes. the start condition is detected as a high to low transition. a dummy start bit is generated in serial expan- sion mode. the start bit is not generated in synchronous mode. data : the data word length is programmable from 5 to 8 bits, for both synchronous and asyn- chronous modes. lsb are transmitted first. parity : the parity bit (not available in serial ex- pansion mode and synchronous mode) is option- al, and can be used with any word length. it is used for error checking and is set so as to make the total number of high bits in data plus parity odd or even, depending on the number of a1os in the data field. address/9th : the address/9th bit is optional and may be added to any word format. it is used in both serial expansion and asynchronous modes to indicate that the data is an address (bit set). the address/9th bit is useful when several mi- crocontrollers are exchanging data on the same serial bus. individual microcontrollers can stay idle on the serial bus, waiting for a transmitted ad- dress. when a microcontroller recognizes its own address, it can begin data reception, likewise, on the transmit side, the microcontroller can transmit another address to begin communication with a different microcontroller. the address/9th bit can be used as an addi- tional data bit or to mark control words (9th bit). stop : indicates the end of a data frame in asyn- chronous modes. a dummy stop bit is generated in serial expansion mode. the stop bit can be programmed to be 1, 1.5, 2, 2.5 or 3 bits long, de- pending on the mode. it returns the sci to the qui- escent marking state (i.e., a constant high-state condition) which lasts until a new start bit indicates an incoming word. the stop bit is not generated in synchronous mode. figure 79. sci character formats (1) lsb first (2) not available in synchronous mode (3) not available in serial expansion mode and synchronous mode start (2) data (1) parity (3) address (2) stop (2) # bits 1 5,6,7,8 0,1 0,1 1, 1.5, 2, 2.5, 1, 2, 3 16x 1x states none odd even on off 9
147/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.4.1 data transfer data to be transmitted by the sci is first loaded by the program into the transmitter buffer register. the sci will transfer the data into the transmitter shift register when the shift register becomes available (empty). the transmitter shift register converts the parallel data into serial format for transmission via the sci alternate function out- put, serial data out. on completion of the transfer, the transmitter buffer register interrupt pending bit will be updated. if the selected word length is less than 8 bits, the unused most significant bits do not need to be defined. incoming serial data from the serial data input pin is converted into parallel format by the receiver shift register. at the end of the input data frame, the valid data portion of the received word is trans- ferred from the receiver shift register into the re- ceiver buffer register. all receiver interrupt con- ditions are updated at the time of transfer. if the selected character format is less than 8 bits, the unused most significant bits will be set. the frame control and status block creates and checks the character configuration (data length and number of stop bits), as well as the source of the transmitter/receiver clock. the internal baud rate generator contains a pro- grammable divide by ano counter which can be used to generate the clocks for the transmitter and/or receiver. the baud rate generator can use intclk or the receiver clock input via rxclk. the address bit/d9 is optional and may be added to any word in asynchronous and serial expan- sion modes. it is commonly used in network or ma- chine control applications. when enabled (ab set), an address or ninth data bit can be added to a transmitted word by setting the set address bit (sa). this is then appended to the next word en- tered into the (empty) transmitter buffer register and then cleared by hardware. on character input, a set address bit can indicate that the data pre- ceding the bit is an address which may be com- pared in hardware with the value in the address compare register (acr) to generate an address match interrupt when equal. the address bit and address comparison regis- ter can also be combined to generate four different types of address interrupt to suit different proto- cols, based on the status of the address mode en- able bit (amen) and the address mode bit (am) in the chcr register. the character match address interrupt mode may be used as a powerful character search mode, generating an interrupt on reception of a predeter- mined character e.g. carriage return or end of block codes (character match interrupt). this is the only address interrupt mode available in syn- chronous mode. the line break condition is fully supported for both transmission and reception. line break is sent by setting the sb bit (idpr). this causes the trans- mitter output to be held low (after all buffered data has been transmitted) for a minimum of one com- plete word length and until the sb bit is reset. break cannot be inserted into the transmitted frame for the synchronous mode. testing of the communications channel may be performed using the built-in facilities of the sci pe- ripheral. auto-echo mode and loop-back mode may be used individually or together. in asynchro- nous, asynchronous with synchronous clock and serial expansion modes they are available only on sin/sout pins through the programming of aen/ lben bits in ccr. in synchronous mode (smen set) the above configurations are available on sin/ sout, rxclk/clkout and dcd/rts pins by programming the aen/lben bits and independ- ently of the programmed polarity. in the synchro- nous mode case, when aen is set, the transmitter outputs (data, clock and control) are disconnected from the i/o pins, which are driven directly by the receiver input pins (auto-echo mode: sout=sin, clkout=rxclk and rts=dcd, even if they act on the internal receiver with the programmed po- larity/edge). when lben is set, the receiver inputs (data, clock and controls) are disconnected and the transmitter outputs are looped-back into the re- ceiver section (loop-back mode: sin=sout, rx- clk=clkout, dcd=rts. the output pins are locked to their programmed stand-by level and the status of the inpl, xckpl, dcdpl, outpl, ockpl and rtspl bits in the sicr register are ir- relevant). refer to figure 80, figure 81, and fig- ure 82 for these different configurations. table 27. address interrupt modes (1) not available in synchronous mode if 9th data bit is set (1) if character match if character match and 9th data bit is set (1) if character match immediately follows break (1) 9
148/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) figure 80. auto echo configuration figure 81. loop back configuration figure 82. auto echo and loop-back configuration all modes except synchronous synchronous mode (smen=1) receiver sin sout vr000210 transmitte r receiver sin sout vr00210a trans mitter dcd rts rxclk clkout all modes except synchronous synchronous mode (smen=1) receiver sin sout vr000211 transmitt er logical 1 receiver sin sout vr00211a transmit ter dcd rts rxclk clkout stand-by value stand-by value stand-by value clock data all modes except synchronous synchronous mode (smen=1) receive r sin sout vr000212 transmi tter receiver sin sout vr00212a transmit ter dcd rts rxclk clkout clock data 9
149/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.5 clocks and serial transmission rates the communication bit rate of the sci transmitter and receiver sections can be provided from the in- ternal baud rate generator or from external sources. the bit rate clock is divided by 16 in asynchronous mode (cd in ccr reset), or undi- vided in the 3 other modes (cd set). with intclk running at 24mhz and no external clock provided, a maximum bit rate of 3mbaud and 750kbaud is available in undivided and divide by-16-mode respectively. with intclk running at 24mhz and an external clock provided through the rxclk/txclk lines, a maximum bit rate of 3mbaud and 375kbaud is avaiable in undivided and divided by 16 mode re- spectively (see figure 10 oreceiver and transmit- ter clock frequencieso)o external clock sources. the external clock in- put pin txclk may be programmed by the xtclk and oclk bits in the ccr register as: the transmit clock input, baud rate generator output (allowing an external divider circuit to provide the receive clock for split rate transmit and receive), or as clkout output in synchronous and serial ex- pansion modes. the rxclk receive clock input is enabled by the xrx bit, this input should be set in accordance with the setting of the cd bit. baud rate generator. the internal baud rate generator consists of a 16-bit programmable di- vide by ano counter which can be used to generate the transmitter and/or receiver clocks. the mini- mum baud rate divisor is 2 and the maximum divi- sor is 2 16 -1. after initialising the baud rate genera- tor, the divisor value is immediately loaded into the counter. this prevents potentially long random counts on the initial load. the baud rate generator frequency is equal to the input clock frequency divided by the divisor value. warning: programming the baud rate divider to 0 or 1 will stop the divider. the output of the baud rate generator has a pre- cise 50% duty cycle. the baud rate generator can use intclk for the input clock source. in this case, intclk (and therefore the mcu xtal) should be chosen to provide a suitable frequency for division by the baud rate generator to give the required transmit and receive bit rates. suitable intclk frequencies and the respective divider values for standard baud rates are shown in table 28. 9.5.6 sci initialization procedure writing to either of the two baud rate generator registers immediately disables and resets the sci baud rate generator, as well as the transmitter and receiver circuitry. after writing to the second baud rate generator register, the transmitter and receiver circuits are enabled. the baud rate generator will load the new value and start counting. to initialize the sci, the user should first initialize the most significant byte of the baud rate gener- ator register; this will reset all sci circuitry. the user should then initialize all other sci registers (sicr/socr included) for the desired operating mode and then, to enable the sci, he should ini- tialize the least significant byte baud rate gener- ator register. 'on-the-fly' modifications of the control registers' content during transmitter/receiver operations, al- though possible, can corrupt data and produce un- desirable spikes on the i/o lines (data, clock and control). furthermore, modifying the control regis- ters' content without reinitialising the sci circuitry (during stand-by cycles, waiting to transmit or re- ceive data) must be kept carefully under control by software to avoid spurious data being transmitted or received. note : for synchronous receive operation, the data and receive clock must not exhibit significant skew between clock and data. the received data and clock are internally synchronized to intclk. figure 83. sci baud rate generator initialization sequence select sci working mode least significant byte initializatio n most significant byte initializatio n 9
150/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) table 28. sci baud rate generator divider values example 1 table 29. sci baud rate generator divider values example 2 intclk: 19660.800 khz baud rate clock factor desired freq (khz) divisor actual baud rate actual freq (khz) deviation dec hex 50.00 16 x 0.80000 24576 6000 50.00 0.80000 0.0000% 75.00 16 x 1.20000 16384 4000 75.00 1.20000 0.0000% 110.00 16 x 1.76000 11170 2ba2 110.01 1.76014 -0.00081% 300.00 16 x 4.80000 4096 1000 300.00 4.80000 0.0000% 600.00 16 x 9.60000 2048 800 600.00 9.60000 0.0000% 1200.00 16 x 19.20000 1024 400 1200.00 19.20000 0.0000% 2400.00 16 x 38.40000 512 200 2400.00 38.40000 0.0000% 4800.00 16 x 76.80000 256 100 4800.00 76.80000 0.0000% 9600.00 16 x 153.60000 128 80 9600.00 153.60000 0.0000% 19200.00 16 x 307.20000 64 40 19200.00 307.20000 0.0000% 38400.00 16 x 614.40000 32 20 38400.00 614.40000 0.0000% 76800.00 16 x 1228.80000 16 10 76800.00 1228.80000 0.0000% intclk: 24576 khz baud rate clock factor desired freq (khz) divisor actual baud rate actual freq (khz) deviation dec hex 50.00 16 x 0.80000 30720 7800 50.00 0.80000 0.0000% 75.00 16 x 1.20000 20480 5000 75.00 1.20000 0.0000% 110.00 16 x 1.76000 13963 383b 110.01 1.76014 -0.00046% 300.00 16 x 4.80000 5120 1400 300.00 4.80000 0.0000% 600.00 16 x 9.60000 2560 a00 600.00 9.60000 0.0000% 1200.00 16 x 19.20000 1280 500 1200.00 19.20000 0.0000% 2400.00 16 x 38.40000 640 280 2400.00 38.40000 0.0000% 4800.00 16 x 76.80000 320 140 4800.00 76.80000 0.0000% 9600.00 16 x 153.60000 160 a0 9600.00 153.60000 0.0000% 19200.00 16 x 307.20000 80 50 19200.00 307.20000 0.0000% 38400.00 16 x 614.40000 40 28 38400.00 614.40000 0.0000% 76800.00 16 x 1228.80000 20 14 76800.00 1228.80000 0.0000% 9
151/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.7 input signals sin: serial data input . this pin is the serial data input to the sci receiver shift register. txclk: external transmitter clock input . this pin is the external input clock driving the sci trans- mitter. the txclk frequency must be greater than or equal to 16 times the transmitter data rate (de- pending whether the x16 or the x1 clock have been selected). a 50% duty cycle is required for this input and must have a period of at least twice intclk. the use of the txclk pin is optional. rxclk: external receiver clock input. this in- put is the clock to the sci receiver when using an external clock source connected to the baud rate generator. intclk is normally the clock source. a 50% duty cycle is required for this input and must have a period of at least twice intclk. use of rx- clk is optional. dcd: data carrier detect. this input is enabled only in synchronous mode; it works as a gate for the rxclk clock and informs the mcu that an emitting device is transmitting a synchronous frame. the active level can be programmed as 1 or 0 and must be provided at least one intclk pe- riod before the first active edge of the input clock. 9.5.8 output signals sout: serial data output. this alternate func- tion output signal is the serial data output for the sci transmitter in all operating modes. clkout: clock output . the alternate function of this pin outputs either the data clock from the transmitter in serial expansion or synchronous modes, or the clock output from the baud rate generator. in serial expansion mode it will clock only the data portion of the frame and its stand-by state is high: data is valid on the rising edge of the clock. even in synchronous mode clkout will only clock the data portion of the frame, but the stand-by level and active edge polarity are pro- grammable by the user. when synchronous mode is disabled (smen in sicr is reset), the state of the xtclk and oclk bits in ccr determine the source of clkout; '11' enables the serial expansion mode. when the synchronous mode is enabled (smen in sicr is set), the state of the xtclk and oclk bits in ccr determine the source of clkout; '00' disables it for plm applications. rts: request to send. this output alternate function is only enabled in synchronous mode; it becomes active when the least significant bit of the data frame is sent to the serial output pin (sout) and indicates to the target device that the mcu is about to send a synchronous frame; it re- turns to its stand-by value just after the last active edge of clkout (msb transmitted). the active level can be programmed high or low. sds: synchronous data strobe. this output al- ternate function is only enabled in synchronous mode; it becomes active high when the least sig- nificant bit is sent to the serial output pins (sout) and indicates to the target device that the mcu is about to send the first bit for each synchro- nous frame. it is active high on the first bit and it is low for all the rest of the frame. the active level can not be programmed. figure 84. receiver and transmitter clock frequencies note: the internal receiver and transmitter clocks are the ones applied to the tx and rx shift regis- ters (see figure 75). min max conditions receiver clock frequency external rxclk 0 intclk/8 1x mode 0 intclk/4 16x mode internal receiver clock 0 intclk/8 1x mode 0 intclk/2 16x mode transmitter clock frequency external txclk 0 intclk/8 1x mode 0 intclk/4 16x mode internal transmitter clock 0 intclk/8 1x mode 0 intclk/2 16x mode 9
152/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.9 interrupts and dma 9.5.9.1 interrupts the sci can generate interrupts as a result of sev- eral conditions. receiver interrupts include data pending, receive errors (overrun, framing and par- ity), as well as address or break pending. trans- mitter interrupts are software selectable for either transmit buffer register empty (bsn set) or for transmit shift register empty (bsn reset) condi- tions. typical usage of the interrupts generated by the sci peripheral are illustrated in figure 85. the sci peripheral is able to generate interrupt re- quests as a result of a number of events, several of which share the same interrupt vector. it is therefore necessary to poll s_isr, the interrupt status register, in order to determine the active trigger. these bits should be reset by the program- mer during the interrupt service routine. the four major levels of interrupt are encoded in hardware to provide two bits of the interrupt vector register, allowing the position of the block of point- er vectors to be resolved to an 8 byte block size. the sci interrupts have an internal priority struc- ture in order to resolve simultaneous events. refer also to section 9.5.3 sci operating modes for more details relating to synchronous mode. table 30. sci interrupt internal priority receive dma request highest priority transmit dma request receive interrupt transmit interrupt lowest priority 9
153/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) table 31. sci interrupt vectors figure 85. sci interrupts: example of typical usage interrupt source vector address transmitter buffer or shift register empty transmit dma end of block xxx x110 received data pending receive dma end of block xxxx x100 break detector address word match xxxx x010 receiver error xxxx x000 interrupt break match address data address after break condition address word marked by d9=1 address interrupt interrupt d9=1 d9 acting as data control with separate interrupt character search mode interrupt va00270 break break interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt interrupt interrupt data address data data data data no match address break data no match address match data data data match data char match data data data data address data data d9=1 data data data data 9
154/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.9.2 dma two dma channels are associated with the sci, for transmit and for receive. these follow the reg- ister scheme as described in the dma chapter. dma reception to perform a dma transfer in reception mode: 1. initialize the dma counter (rdcpr) and dma address (rdapr) registers 2. enable dma by setting the rxd bit in the idpr register. 3. dma transfer is started when data is received by the sci. dma transmission to perform a dma transfer in transmission mode: 1. initialize the dma counter (tdcpr) and dma address (tdapr) registers. 2. enable dma by setting the txd bit in the idpr register. 3. dma transfer is started by writing a byte in the transmitter buffer register (txbr). if this byte is the first data byte to be transmitted, the dma counter and address registers must be initialized to begin dma transmission at the sec- ond byte. alternatively, dma transfer can be start- ed by writing a dummy byte in the txbr register. dma interrupts when dma is active, the received data pending and the transmitter shift register empty interrupt sources are replaced by the dma end of block re- ceive and transmit interrupt sources. note: to handle dma transfer correctly in trans- mission, the bsn bit in the imr register must be cleared. this selects the transmitter shift register empty event as the dma interrupt source. the transfer of the last byte of a dma data block will be followed by a dma end of block transmit or receive interrupt, setting the txeob or rxeob bit. a typical transmission end of block interrupt rou- tine will perform the following actions: 1. restore the dma counter register (tdcpr). 2. restore the dma address register (tdapr). 3. clear the transmitter shift register empty bit txsem in the s_isr register to avoid spurious interrupts. 4. clear the transmitter end of block (txeob) pending bit in the imr register. 5. set the txd bit in the idpr register to enable dma. 6. load the transmitter buffer register (txbr) with the next byte to transmit. the above procedure handles the case where a further dma transfer is to be performed. error interrupt handling if an error interrupt occurs while dma is enabled in reception mode, dma transfer is stopped. to resume dma transfer, the error interrupt han- dling routine must clear the corresponding error flag. in the case of an overrun error, the routine must also read the rxbr register. character search mode with dma in character search mode with dma, when a character match occurs, this character is not trans- ferred. dma continues with the next received char- acter. to avoid an overrun error occurring, the character match interrupt service routine must read the rxbr register. 9
155/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) 9.5.10 register description the sci registers are located in the following pag- es in the st9: sci number 0: page 24 (18h) sci number 1: page 25 (19h) (when present) the sci is controlled by the following registers: address register r240 (f0h) receiver dma transaction counter pointer register r241 (f1h) receiver dma source address pointer register r242 (f2h) transmitter dma transaction counter pointer register r243 (f3h) transmitter dma destination address pointer register r244 (f4h) interrupt vector register r245 (f5h) address compare register r246 (f6h) interrupt mask register r247 (f7h) interrupt status register r248 (f8h) receive buffer register same address as transmitter buffer register (read only) r248 (f8h) transmitter buffer register same address as receive buffer register (write only) r249 (f9h) interrupt/dma priority register r250 (fah) character configuration register r251 (fbh) clock configuration register r252 (fch) baud rate generator high register r253 (fdh) baud rate generator low register r254 (feh) synchronous input control register r255 (ffh) synchronous output control register 9
156/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) receiver dma counter pointer (rdcpr) r240 - read/write reset value: undefined bit 7:1 = rc[7:1] : receiver dma counter pointer. these bits contain the address of the receiver dma transaction counter in the register file. bit 0 = rr/m : receiver register file/memory se- lector . 0: select memory space as destination. 1: select the register file as destination. receiver dma address pointer (rdapr) r241 - read/write reset value: undefined bit 7:1 = ra[7:1] : receiver dma address pointer. these bits contain the address of the pointer (in the register file) of the receiver dma data source. bit 0 = rps : receiver dma memory pointer se- lector. this bit is only significant if memory has been se- lected for dma transfers (rr/m = 0 in the rdcpr register). 0: select isr register for receiver dma transfers address extension. 1: select dmasr register for receiver dma trans- fers address extension. transmitter dma counter pointer (tdcpr) r242 - read/write reset value: undefined bit 7:1 = tc[7:1] : transmitter dma counter point- er . these bits contain the address of the transmitter dma transaction counter in the register file. bit 0 = tr/m : transmitter register file/memory selector . 0: select memory space as source. 1: select the register file as source. transmitter dma address pointer (tdapr) r243 - read/write reset value: undefined bit 7:1 = ta[7:1] : transmitter dma address point- er. these bits contain the address of the pointer (in the register file) of the transmitter dma data source. bit 0 = tps : transmitter dma memory pointer se- lector. this bit is only significant if memory has been se- lected for dma transfers (tr/m = 0 in the tdcpr register). 0: select isr register for transmitter dma transfers address extension. 1: select dmasr register for transmitter dma transfers address extension. 70 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rr/m 70 ra7 ra6 ra5 ra4 ra3 ra2 ra1 rps 70 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tr/m 70 ta7 ta6 ta5 ta4 ta3 ta2 ta1 tps 9
157/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) interrupt vector register (s_ivr) r244 - read/write reset value: undefined bit 7:3 = v[7:3] : sci interrupt vector base ad- dress. user programmable interrupt vector bits for trans- mitter and receiver. bit 2:1 = ev[2:1] : encoded interrupt source. both bits ev2 and ev1 are read only and set by hardware according to the interrupt source. bit 0 = d0 : this bit is forced by hardware to 0. address/data compare register (acr) r245 - read/write reset value: undefined bit 7:0 = ac[7:0] : address/compare character . with either 9th bit address mode, address after break mode, or character search, the received ad- dress will be compared to the value stored in this register. when a valid address matches this regis- ter content, the receiver address pending bit (rxap in the s_isr register) is set. after the rxap bit is set in an addressed mode, all received data words will be transferred to the receiver buff- er register. 70 v7 v6 v5 v4 v3 ev2 ev1 0 ev2 ev1 interrupt source 0 0 receiver error (overrun, framing, parity) 0 1 break detect or address match 10 received data pending/receiver dma end of block 11 transmitter buffer or shift register empty transmitter dma end of block 70 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 9
158/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) interrupt mask register (imr) r246 - read/write reset value: 0xx00000 bit 7 = bsn : buffer or shift register empty inter- rupt . this bit selects the source of the transmitter regis- ter empty interrupt. 0: select a shift register empty as source of a transmitter register empty interrupt. 1: select a buffer register empty as source of a transmitter register empty interrupt. bit 6 = rxeob : received end of block. this bit is set by hardware only and must be reset by software. rxeob is set after a receiver dma cycle to mark the end of a data block. 0: clear the interrupt request. 1: mark the end of a received block of data. bit 5 = txeob : transmitter end of block. this bit is set by hardware only and must be reset by software. txeob is set after a transmitter dma cycle to mark the end of a data block. 0: clear the interrupt request. 1: mark the end of a transmitted block of data. bit 4 = rxe : receiver error mask. 0: disable receiver error interrupts (oe, pe, and fe pending bits in the s_isr register). 1: enable receiver error interrupts. bit 3 = rxa : receiver address mask . 0: disable receiver address interrupt (rxap pending bit in the s_isr register). 1: enable receiver address interrupt. bit 2 = rxb : receiver break mask . 0: disable receiver break interrupt (rxbp pend- ing bit in the s_isr register). 1: enable receiver break interrupt. bit 1 = rxdi : receiver data interrupt mask . 0: disable receiver data pending and receiver end of block interrupts (rxdp and rxeob pending bits in the s_isr register). 1: enable receiver data pending and receiver end of block interrupts. note: rxdi has no effect on dma transfers. bit 0 = txdi : transmitter data interrupt mask . 0: disable transmitter buffer register empty, transmitter shift register empty, or transmitter end of block interrupts (txbem, txsem, and txeob bits in the s_isr register). 1: enable transmitter buffer register empty, transmitter shift register empty, or transmitter end of block interrupts. note: txdi has no effect on dma transfers. 70 bsn rxeob txeob rxe rxa rxb rxdi txdi 9
159/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) interrupt status register (s_isr) r247 - read/write reset value: undefined bit 7 = oe : overrun error pending . this bit is set by hardware if the data in the receiv- er buffer register was not read by the cpu before the next character was transferred into the receiv- er buffer register (the previous data is lost). 0: no overrun error. 1: overrun error occurred. bit 6 = fe : framing error pending bit . this bit is set by hardware if the received data word did not have a valid stop bit. 0: no framing error. 1: framing error occurred. note: in the case where a framing error occurs when the sci is programmed in address mode and is monitoring an address, the interrupt is as- serted and the corrupted data element is trans- ferred to the receiver buffer register. bit 5 = pe : parity error pending . this bit is set by hardware if the received word did not have the correct even or odd parity bit. 0: no parity error. 1: parity error occurred. bit 4 = rxap : receiver address pending . rxap is set by hardware after an interrupt ac- knowledged in the address mode. 0: no interrupt in address mode. 1: interrupt in address mode occurred. note: the source of this interrupt is given by the couple of bits (amen, am) as detailed in the idpr register description. bit 3 = rxbp : receiver break pending bit . this bit is set by hardware if the received data in- put is held low for the full word transmission time (start bit, data bits, parity bit, stop bit). 0: no break received. 1: break event occurred. bit 2 = rxdp : receiver data pending bit. this bit is set by hardware when data is loaded into the receiver buffer register. 0: no data received. 1: data received in receiver buffer register. bit 1 = txbem : transmitter buffer register emp- ty . this bit is set by hardware if the buffer register is empty. 0: no buffer register empty event. 1: buffer register empty. bit 0 = txsem : transmitter shift register empty . this bit is set by hardware if the shift register has completed the transmission of the available data. 0: no shift register empty event. 1: shift register empty. note: the interrupt status register bits can be re- set but cannot be set by the user. the interrupt source must be cleared by resetting the related bit when executing the interrupt service routine (natu- rally the other pending bits should not be reset). 70 oe fe pe rxap rxbp rxdp txbe m txsem 9
160/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) receiver buffer register (rxbr) r248 - read only reset value: undefined bit 7:0 = rd[7:0] : received data. this register stores the data portion of the re- ceived word. the data will be transferred from the receiver shift register into the receiver buffer register at the end of the word. all receiver inter- rupt conditions will be updated at the time of trans- fer. if the selected character format is less than 8 bits, unused most significant bits will forced to a1o. note: rxbr and txbr are two physically differ- ent registers located at the same address. transmitter buffer register (txbr) r248 - write only reset value: undefined bit 7:0 = td[7:0] : transmit data . the st9 core will load the data for transmission into this register. the sci will transfer the data from the buffer into the shift register when availa- ble. at the transfer, the transmitter buffer register interrupt is updated. if the selected word format is less than 8 bits, the unused most significant bits are not significant. note: txbr and rxbr are two physically differ- ent registers located at the same address. 70 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 70 td7 td6 td5 td4 td3 td2 td1 td0 9
161/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) interrupt/dma priority register (idpr) r249 - read/write reset value: undefined bit 7 = amen : address mode enable. this bit, together with the am bit (in the chcr reg- ister), decodes the desired addressing/9th data bit/character match operation. in address mode the sci monitors the input serial data until its address is detected note: upon reception of address, the rxap bit (in the interrupt status register) is set and an inter- rupt cycle can begin. the address character will not be transferred into the receiver buffer regis- ter but all data following the matched sci address and preceding the next address word will be trans- ferred to the receiver buffer register and the proper interrupts updated. if the address does not match, all data following this unmatched address will not be transferred to the receiver buffer reg- ister. in any of the cases the rxap bit must be reset by software before the next word is transferred into the buffer register. when amen is reset and am is set, a useful char- acter search function is performed. this allows the sci to generate an interrupt whenever a specific character is encountered (e.g. carriage return). bit 6 = sb : set break . 0: stop the break transmission after minimum break length. 1: transmit a break following the transmission of all data in the transmitter shift register and the buffer register. note: the break will be a low level on the transmit- ter data output for at least one complete word for- mat. if software does not reset sb before the min- imum break length has finished, the break condi- tion will continue until software resets sb. the sci terminates the break condition with a high level on the transmitter data output for one transmission clock period. bit 5 = sa : set address . if an address/9th data bit mode is selected, sa val- ue will be loaded for transmission into the shift register. this bit is cleared by hardware after its load. 0: indicate it is not an address word. 1: indicate an address word. note: proper procedure would be, when the transmitter buffer register is empty, to load the value of sa and then load the data into the trans- mitter buffer register. bit 4 = rxd : receiver dma mask . this bit is reset by hardware when the transaction counter value decrements to zero. at that time a receiver end of block interrupt can occur. 0: disable receiver dma request (the rxdp bit in the s_isr register can request an interrupt). 1: enable receiver dma request (the rxdp bit in the s_isr register can request a dma transfer). bit 3 = txd : transmitter dma mask . this bit is reset by hardware when the transaction counter value decrements to zero. at that time a transmitter end of block interrupt can occur. 0: disable transmitter dma request (txbem or txsem bits in s_isr can request an interrupt). 1: enable transmitter dma request (txbem or txsem bits in s_isr can request a dma trans- fer). bit 2:0 = prl[2:0] : sci interrupt/dma priority bits . the priority for the sci is encoded with (prl2,prl1,prl0). priority level 0 is the highest, while level 7 represents no priority. when the user has defined a priority level for the sci, priorities within the sci are hardware defined. these sci internal priorities are: 70 amen sb sa rxd txd prl2 prl1 prl0 amen am 0 0 address interrupt if 9th data bit = 1 0 1 address interrupt if character match 10 address interrupt if character match and 9th data bit =1 11 address interrupt if character match with word immediately following break receiver dma request highest priority transmitter dma request receiver interrupt transmitter interrupt lowest priority 9
162/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) character configuration register (chcr) r250 - read/write reset value: undefined bit 7 = am : address mode . this bit, together with the amen bit (in the idpr register), decodes the desired addressing/9th data bit/character match operation. please refer to the table in the idpr register description. bit 6 = ep : even parity . 0: select odd parity (when parity is enabled). 1: select even parity (when parity is enabled). bit 5 = pen : parity enable . 0: no parity bit. 1: parity bit generated (transmit data) or checked (received data). note: if the address/9th bit is enabled, the parity bit will precede the address/9th bit (the 9th bit is never included in the parity calculation). bit 4 = ab : address/9th bit . 0: no address/9th bit. 1: address/9th bit included in the character format between the parity bit and the first stop bit. this bit can be used to address the sci or as a ninth data bit. bit 3:2 = sb[1:0] : number of stop bits .. bit 1:0 = wl[1:0] : number of data bits 70 am ep pen ab sb1 sb0 wl1 wl0 sb1 sb0 number of stop bits in 16x mode in 1x mode 00 1 1 0 1 1.5 2 10 2 2 1 1 2.5 3 wl1 wl0 data length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits 9
163/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) clock configuration register (ccr) r251 - read/write reset value: 0000 0000 (00h) bit 7 = xtclk this bit, together with the oclk bit, selects the source for the transmitter clock. the following ta- ble shows the coding of xtclk and oclk. bit 6 = oclk this bit, together with the xtclk bit, selects the source for the transmitter clock. the following ta- ble shows the coding of xtclk and oclk. bit 5 = xrx : external receiver clock source . 0: external receiver clock source not used. 1: select the external receiver clock source. note: the external receiver clock frequency must be 16 times the data rate, or equal to the data rate, depending on the status of the cd bit. bit 4 = xbrg : baud rate generator clock source . 0: select intclk for the baud rate generator. 1: select the external receiver clock for the baud rate generator. bit 3 = cd : clock divisor . the status of cd will determine the sci configura- tion (synchronous/asynchronous). 0: select 16x clock mode for both receiver and transmitter. 1: select 1x clock mode for both receiver and transmitter. note: in 1x clock mode, the transmitter will trans- mit data at one data bit per clock period. in 16x mode each data bit period will be 16 clock periods long. bit 2 = aen : auto echo enable . 0: no auto echo mode. 1: put the sci in auto echo mode. note: auto echo mode has the following effect: the sci transmitter is disconnected from the data- out pin sout, which is driven directly by the re- ceiver data-in pin, sin. the receiver remains con- nected to sin and is operational, unless loopback mode is also selected. bit 1 = lben : loopback enable . 0: no loopback mode. 1: put the sci in loopback mode. note: in this mode, the transmitter output is set to a high level, the receiver input is disconnected, and the output of the transmitter shift register is looped back into the receiver shift register input. all interrupt sources (transmitter and receiver) are operational. bit 0 = stpen : stick parity enable . 0: the transmitter and the receiver will follow the parity of even parity bit ep in the chcr register. 1: the transmitter and the receiver will use the op- posite parity type selected by the even parity bit ep in the chcr register. 70 xtclk oclk xrx xbrg cd aen lben stpe n xtclk oclk pin function 0 0 pin is used as a general i/o 0 1 pin = txclk (used as an input) 10 pin = clkout (outputs the baud rate generator clock) 11 pin = clkout (outputs the serial expansion and synchronous mode clock) ep spen parity (transmitter & receiver) 0 (odd) 0 odd 1 (even) 0 even 0 (odd) 1 even 1 (even) 1 odd 9
164/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) baud rate generator high register (brghr) r252 - read/write reset value: undefined baud rate generator low register (brglr) r253 - read/write reset value: undefined bit 15:0 = baud rate generator msb and lsb. the baud rate generator is a programmable di- vide by ano counter which can be used to generate the clocks for the transmitter and/or receiver. this counter divides the clock input by the value in the baud rate generator register. the minimum baud rate divisor is 2 and the maximum divisor is 2 16 -1. after initialization of the baud rate genera- tor, the divisor value is immediately loaded into the counter. this prevents potentially long random counts on the initial load. if set to 0 or 1, the baud rate generator is stopped. synchronous input control (sicr) r254 - read/write reset value: 0000 0011 (03h) bit 7 = smen : synchronous mode enable . 0: disable all features relating to synchronous mode (the contents of sicr and socr are ig- nored). 1: select synchronous mode with its programmed i/o configuration. bit 6 = inpl : sin input polarity . 0: polarity not inverted. 1: polarity inverted. note: inpl only affects received data. in auto- echo mode sout = sin even if inpl is set. in loop-back mode the state of the inpl bit is irrele- vant. bit 5 = xckpl : receiver clock polarity . 0: rxclk is active on the rising edge. 1: rxclk is active on the falling edge. note: xckpl only affects the receiver clock. in auto-echo mode clkout = rxclk independ- ently of the xckpl status. in loop-back the state of the xckpl bit is irrelevant. bit 4 = dcden : dcd input enable . 0: disable hardware synchronization. 1: enable hardware synchronization. note: when dcden is set, rxclk drives the re- ceiver section only during the active level of the dcd input (dcd works as a gate on rxclk, in- forming the mcu that a transmitting device is sending a synchronous frame to it). bit 3 = dcdpl : dcd input polarity . 0: the dcd input is active when low. 1: the dcd input is active when high. note: dcdpl only affects the gating activity of the receiver clock. in auto-echo mode rts = dcd in- dependently of dcdpl. in loop-back mode, the state of dcdpl is irrelevant. bit 2 = inpen : all input disable . 0: enable sin/rxclk/dcd inputs. 1: disable sin/rxclk/dcd inputs. bit 1:0 = adon't careo 15 8 bg15 bg14 bg13 bg12 bg11 bg10 bg9 bg8 70 bg7 bg6 bg5 bg4 bg3 bg2 bg1 bg0 70 smen inpl xckpl dcde n dcdp l inpen x x 9
165/190 st90158 - serial communications interface (sci) serial communications interface (cont'd) synchronous output control (socr) r255 - read/write reset value: 0000 0001 (01h) bit 7 = outpl : sout output polarity. 0: polarity not inverted. 1: polarity inverted. note: outpl only affects the data sent by the transmitter section. in auto-echo mode sout = sin even if outpl=1. in loop-back mode, the state of outpl is irrelevant. bit 6 = outsb : sout output stand-by level . 0: sout stand-by level is high. 1: sout stand-by level is low. bit 5 = ockpl : transmitter clock polarity. 0: clkout is active on the rising edge. 1: clkout is active on the falling edge. note: ockpl only affects the transmitter clock. in auto-echo mode clkout = rxclk independ- ently of the state of ockpl. in loop-back mode the state of ockpl is irrelevant. bit 4 = ocksb : transmitter clock stand-by lev- el. 0: the clkout stand-by level is high. 1: the clkout stand-by level is low. bit 3 = rtsen : rts and sds output enable . 0: disable the rts and sds hardware synchroni- sation. 1: enable the rts and sds hardware synchroni- sation. notes: when rtsen is set, the rts output becomes active just before the first active edge of clk- out and indicates to target device that the mcu is about to send a synchronous frame; it returns to its stand-by value just after the last active edge of clkout (msb transmitted). when rtsen is set, the sds output becomes active high and indicates to the target device that the mcu is about to send the first bit of a syn- chronous frame on the serial output pin (sout); it returns to low level as soon as the second bit is sent on the serial output pin (sout). in this way a positive pulse is generated each time that the first bit of a synchronous frame is present on the serial output pin (sout). bit 2 = rtspl : rts output polarity. 0: the rts output is active when low. 1: the rts output is active when high. note: rtspl only affects the rts activity on the output pin. in auto-echo mode rts = dcd inde- pendently from the rtspl value. in loop-back mode rtspl value is 'don't care'. bit 1 = outdis : disable all outputs. this feature is available on specific devices only (see device pin-out description). when outdis=1, all output pins (if configured in alternate function mode) will be put in high im- pedance for networking. 0: sout/clkout/enabled 1: sout/clkout/rts put in high impedance bit 0 = adon't careo 70 outp l outs b ockp l ocks b rtse n rts pl out dis x 9
166/190 st90158 - eight-channel analog to digital converter (a/d) 9.6 eight-channel analog to digital converter (a/d) 9.6.1 introduction the 8-channel analog to digital converter (a/d) comprises an input multiplex channel selector feeding a successive approximation converter. conversion requires 138 intclk cycles (of which 84 are required for sampling), conversion time is thus a function of the intclk frequency; for in- stance, for a 20mhz clock rate, conversion of the selected channel requires 6.9 m s. this time in- cludes the 4.2 m s required by the built-in sample and hold circuitry, which minimizes the need for external components and allows quick sampling of the signal to minimise warping and conversion er- ror. conversion resolution is 8 bits, with 1 lsb maximum error in the input range between v ss and the analog v dd reference. the converter uses a fully differential analog input configuration for the best noise immunity and pre- cision performance. two separate supply refer- ences are provided to ensure the best possible supply noise rejection. in fact, the converted digital value, is referred to the analog reference voltage which determines the full scale converted value. naturally , analog and digital v ss must be com- mon. if analog supplies are not present, input ref- erence voltages are referred to the digital ground and supply. up to 8 multiplexed analog inputs are available, depending on the specific device type. a group of signals can be converted sequentially by simply programming the starting address of the first ana- log channel to be converted and with the auto- scan feature. two analog watchdogs are provided, allowing continuous hardware monitoring of two input chan- nels. an interrupt request is generated whenever the converted value of either of these two analog inputs is outside the upper or lower programmed threshold values. the comparison result is stored in a dedicated register. figure 86. block diagram n interrupt unit int. vector pointer int. control register compare result register threshold register threshold register threshold register threshold register 7u 7l 6u 6l compare logic data register 7 data register 6 data register 5 data register 4 data register 3 data register 2 data register 1 data register 0 successive approximation a/d converter analog mux ain 7 ain 6 ain 5 ain 4 ain 3 ain 2 ain 1 ain 0 conversion result autoscan logic control reg. control logic internal trigger external trigger va00223 9
167/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) single and continuous conversion modes are available. conversion may be triggered by an ex- ternal signal or, internally, by the multifunction timer. a power-down programmable bit allows the a/d to be set in low-power idle mode. the a/d's interrupt unit provides two maskable channels (analog watchdog and end of conver- sion) with hardware fixed priority, and up to 7 pro- grammable priority levels. caution : a/d input pin configuration the input analog channel is selected by using the i/o pin alternate function setting (pxc2, pxc1, pxc0 = 1,1,1) as described in the i/o ports sec- tion. the i/o pin configuration of the port connect- ed to the a/d converter is modified in order to pre- vent the analog voltage present on the i/o pin from causing high power dissipation across the input buffer. deselected analog channels should also be maintained in alternate function configuration for the same reason. 9.6.2 functional description 9.6.2.1 operating modes two operating modes are available: continuous mode and single mode. to enter one of these modes it is necessary to program the cont bit of the control logic register. continuous mode is selected when cont is set, while single mode is selected when cont is reset. both modes operate in autoscan configuration, allowing sequential conversion of the input chan- nels. the number of analog inputs to be converted may be set by software, by setting the number of the first channel to be converted into the control register (sc2, sc1, sc0 bits). as each conver- sion is completed, the channel number is automat- ically incremented, up to channel 7. for example, if sc2, sc1, sc0 are set to 0,1,1, conversion will proceed from channel 3 to channel 7, whereas, if sc2, sc1, sc0 are set to 1,1,1, only channel 7 will be converted. when the st bit of the control logic register is set, either by software or by hardware (by an inter- nal or external synchronisation trigger signal), the analog inputs are sequentially converted (from the first selected channel up to channel 7) and the re- sults are stored in the relevant data registers. in single mode (cont = a0o), the st bit is reset by hardware following conversion of channel 7; an end of conversion (ecv) interrupt request is is- sued and the a/d waits for a new start event. in continuous mode (cont = a1o), a continuous conversion flow is initiated by the start event. when conversion of channel 7 is complete, con- version of channel 's' is initiated (where 's' is spec- ified by the setting of the sc2, sc1 and sc0 bits); this will continue until the st bit is reset by soft- ware. in all cases, an ecv interrupt is issued each time channel 7 conversion ends. when channel 'i' is converted ('s' <'i' <7), the relat- ed data register is reloaded with the new conver- sion result and the previous value is lost. the end of conversion (ecv) interrupt service routine can be used to save the current values before a new conversion sequence (so as to create signal sam- ple tables in the register file or in memory). 9.6.2.2 triggering and synchronisation in both modes, conversion may be triggered by in- ternal or external conditions; externally this may be tied to extrg, as an alternate function input on an i/o port pin, and internally, it may be tied to intrg, generated by a multifunction timer pe- ripheral. both external and internal events can be separately masked by programming the extg/ intg bits of the control logic register (clr). the events are internally ored, thus avoiding potential hardware conflicts. however, the correct proce- dure is to enable only one alternate synchronisa- tion condition at any time. the effect either of these synchronisation modes is to set the st bit by hardware. this bit is reset, in single mode only, at the end of each group of con- versions. in continuous mode, all trigger pulses after the first are ignored. the synchronisation sources must be at a logic low level for at least the duration of one intclk cycle and, in single mode, the period between trig- ger pulses must be greater than the total time re- quired for a group of conversions. if a trigger oc- curs when the st bit is still set, i.e. when conver- sion is still in progress, it will be ignored. on devices where two a/d converters are present they can be triggered from the same source. 9.6.2.3 analog watchdogs two internal analog watchdogs are available for highly flexible automatic threshold monitoring of external analog signal levels. converter external trigger on chip event (internal trigger) a/d 0 extrg pin mft 0 a/d 1 9
168/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) analog channels 6 and 7 monitor an acceptable voltage level window for the converted analog in- puts. the external voltages applied to inputs 6 and 7 are considered normal while they remain below their respective upper thresholds, and above or at their respective lower thresholds. when the external signal voltage level is greater than, or equal to, the upper programmed voltage limit, or when it is less than the lower programmed voltage limit, a maskable interrupt request is gen- erated and the compare results register is up- dated in order to flag the threshold (upper or low- er) and channel (6 or 7) responsible for the inter- rupt. the four threshold voltages are user pro- grammable in dedicated registers (08h to 0bh) of the a/d register page. only the 4 msbs of the compare results register are used as flags (the 4 lsbs always return a1o if read), each of the four msbs being associated with a threshold condition. following a hardware reset, these flags are reset. during normal a/d operation, the crr bits are set, in order to flag an out of range condition and are automatically reset by hardware after a software reset of the analog watchdog request flag in the ad_icr register. 9.6.2.4 power down mode before enabling an a/d conversion, the pow bit of the control logic register must be set; this must be done at least 60 m s before the first conversion start, in order to correctly bias the analog section of the converter circuitry. when the a/d is not required, the pow bit may be reset in order to reduce the total power consump- tion. this is the reset configuration, and this state is also selected automatically when the st9 is placed in halt mode (following the execution of the halt instruction). figure 87. a/d trigger source n analog voltage upper threshold lower threshold normal area (window guarded) 9
169/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) figure 88. application example: analog watchdog used in motorspeed control n 9.6.3 interrupts the a/d provides two interrupt sources: end of conversion analog watchdog request the a/d interrupt vector register (ad_ivr) pro- vides hardware generated flags which indicate the interrupt source, thus allowing automatic selection of the correct interrupt service routine. the a/d interrupt vector should be programmed by the user to point to the first memory location in the interrupt vector table containing the base ad- dress of the four byte area of the interrupt vector table in which the address of the a/d interrupt service routines are stored. the analog watchdog interrupt pending bit (awd, ad_icr.6), is automatically set by hardware whenever any of the two guarded analog inputs go out of range. the compare result register (crr) tracks the analog inputs which exceed their pro- grammed thresholds. when two requests occur simultaneously, the an- alog watchdog request has priority over the end of conversion request, which is held pending. the analog watchdog request requires the user to poll the compare result register (crr) to de- termine which of the four thresholds has been ex- ceeded. the threshold status bits are set to flag an out of range condition, and are automatically reset by hardware after a software reset of the analog watchdog request flag in the ad_icr register. the interrupt pending flags, ecv and awd, should be reset by the user within the interrupt service routine. setting either of these two bits by software will cause an interrupt request to be gen- erated. 9.6.3.1 register mapping it is possible to have two independent a/d convert- ers in the same device. in this case they are named a/d 0 and a/d 1. if the device has one a/d converter it uses the register addresses of a/d 0. the register pages are the following: analog watch- dog re- quest 70 lower word address xxxxxx 0 0 end of conv. request 70 upper word address xxxxxx 1 0 a/dn register page a/d 0 63 a/d 1 61 9
170/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) 9.6.4 register description data registers (dir) the conversion results for the 8 available chan- nels are loaded into the 8 data registers following conversion of the corresponding analog input. channel 0 data register (d0r) r240 - read/write register page: 63 reset value: undefined bit 7:0 = d0.[7:0] : channel 0 data. channel 1 data register (d1r) r241 - read/write register page: 63 reset value: undefined bit 7:0 = d1.[7:0] : channel 1 data. channel 2 data register (d2r) r242 - read/write register page: 63 reset value: undefined bit 7:0 = d2.[7:0] : channel 2 data. channel 3 data register (d3r) r243 - read/write register page: 63 reset value: undefined bit 7:0 = d3.[7:0] : channel 3 data. channel 4 data register (d4r) r244 - read/write register page: 63 reset value: undefined bit 7:0 = d4.[7:0] : channel 4 data channel 5 data register (d5r) r245 - read/write register page: 63 reset value: undefined bit 7:0 = d5.[7:0] : channel 5 data . channel 6 data register (d6r) r246 - read/write register page: 63 reset value: undefined bit 7:0 = d6.[7:0] : channel 6 data channel 7 data register (d7r) r247 - read/write register page: 63 reset value: undefined 70 d0.7 d0.6 d0.5 d0.4 d0.3 d0.2 d0.1 d0.0 70 d1.7 d1.6 d1.5 d1.4 d1.3 d1.2 d1.1 d1.0 70 d2.7 d2.6 d2.5 d2.4 d2.3 d2.2 d2.1 d2.0 70 d3.7 d3.6 d3.5 d3.4 d3.3 d3.2 d3.1 d3.0 70 d4.7 d4.6 d4.5 d4.4 d4.3 d4.2 d4.1 d4.0 70 d5.7 d5.6 d5.5 d5.4 d5.3 d5.2 d5.1 d5.0 70 d6.7 d6.6 d6.5 d6.4 d6.3 d6.2 d6.1 d6.0 70 d7.7 d7.6 d7.5 d7.4 d7.3 d7.2 d7.1 d7.0 9
171/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) channel 6 lower threshold register (lt6r) r248 - read/write register page: 63 reset value: undefined bit 7:0 = lt6.[7:0]: channel 6 lower threshold user-defined lower threshold value for channel 6, to be compared with the conversion results. channel 7 lower threshold register (lt7r) r249 - read/write register page: 63 reset value: undefined bit 7:0 = lt7.[7:0]: channel 7 lower threshold. user-defined lower threshold value for channel 7, to be compared with the conversion results. channel 6 upper threshold register (ut6r) r250 - read/write register page: 63 reset value: undefined bit 7:0 = ut6.[7:0] : channel 6 upper threshold value. user-defined upper threshold value for channel 6, to be compared with the conversion results. channel 7 upper threshold register (ut7r) r251 - read/write register page: 63 reset value: undefined bit 7:0 = ut7.[7:0] : channel 7 upper threshold value user-defined upper threshold value for channel 7, to be compared with the conversion results. compare result register (crr) r252 - read/write register page: 63 reset value: 0000 1111 (0fh) these bits are set by hardware and cleared by software. bit 7 = c7u : compare reg 7 upper threshold 0: threshold not reached 1: channel 7 converted data is greater than or equal to ut7r threshold register value. bit 6 = c6u : compare reg 6upper threshold 0: threshold not reached 1: channel 6 converted data is greater than or equal to ut6r threshold register value. bit 5 = c7l : compare reg 7 lower threshold 0: threshold not reached 1: channel 7 converted data is less than the lt7r threshold register value. bit 4 = c6l : compare reg 6 lower threshold 0: threshold not reached 1: channel 6 converted data is less than the lt6r threshold register value. bit 3:0 = reserved, returns a1o when read. note : any software reset request generated by writing to the ad_icr, will also cause all the com- pare status bits to be cleared. 70 lt6.7 lt6.6 lt6.5 lt6.4 lt6.3 lt6.2 lt6.1 lt6.0 70 lt7.7 lt7.6 lt7.5 lt7.4 lt7.3 lt7.2 lt7.1 lt7.0 70 ut6. 7 ut6. 6 ut6. 5 ut6. 4 ut6. 3 ut6. 2 ut6. 1 ut6. 0 70 ut7. 7 ut7. 6 ut7. 5 ut7. 4 ut7. 3 ut7. 2 ut7. 1 ut7. 0 70 c7u c6u c7l c6l 1 1 1 1 9
172/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) control logic register (clr) the control logic register (clr) manages the a/d converter logic. writing to this register will cause the current conversion to be aborted and the autoscan logic to be re-initialized. control logic register (clr) r253 - read/write register page: 63 reset value: 0000 0000 (00h) bit 7:5 = sc[2:0]: start conversion address . these 3 bits define the starting analog input chan- nel (autoscan mode). the first channel addressed by sc[2:0] is converted, then the channel number is incremented for the successive conversion, until channel 7 (111) is converted. when sc2, sc1 and sc0 are all set, only channel 7 will be converted. bit 4 = extg : external trigger enable . this bit is set and cleared by software. 0: external trigger disabled. 1: external trigger enabled. allows a conversion sequence to be started on the subsequent edge of the external signal applied to the extrg pin (when enabled as an alternate function). bit 3 = intg : internal trigger enable . this bit is set and cleared by software. 0: internal trigger disabled. 1: internal trigger enabled. allows a conversion se- quence to be started, synchronized by an inter- nal signal (on-chip event signal) from a multi- function timer peripheral. both external and internal trigger inputs are inter- nally ored, thus avoiding hardware conflicts; however, the correct procedure is to enable only one alternate synchronization input at a time. note: the effect of either synchronization mode is to set the start/stop bit, which is reset by hard- ware when in single mode, at the end of each sequence of conversions. requirements: the external synchronisation in- put must receive a low level pulse longer than an intclk period and, for both external and on-chip event synchronisation, the repetition period must be greater than the time required for the selected sequence of conversions. bit 2 = pow : power up/power down. this bit is set and cleared by software. 0: power down mode: all power-consuming logic is disabled, thus selecting a low power idle mode. 1: power up mode: the a/d converter logic and an- alog circuitry is enabled. bit 1 = cont : continuous/single . 0: single mode: a single sequence of conversions is initiated whenever an external (or internal) trigger occurs, or when the st bit is set by soft- ware. 1: continuous mode: the first sequence of conver- sions is started, either by software (by setting the st bit), or by hardware (on an internal or ex- ternal trigger, depending on the setting of the intg and extg bits); a continuous conversion sequence is then initiated. bit 0 = st : start/stop. 0: stop conversion. when the a/d converter is running in single mode, this bit is hardware re- set at the end of a sequence of conversions. 1: start a sequence of conversions. 70 sc2 sc1 sc0 ext g intg pow con t st 9
173/190 st90158 - eight-channel analog to digital converter (a/d) analog to digital converter (cont'd) interrupt control register (ad_icr) r254 - read/write register page: 63 reset value: 0000 1111 (0fh) bit 7 = ecv : end of conversion. this bit is set by hardware after a group of conver- sions is completed. it must be reset by the user, before returning from the interrupt service rou- tine. setting this bit by software will cause a soft- ware interrupt request to be generated. 0: no end of conversion event occurred 1: an end of conversion event occurred bit 6 = awd : analog watchdog. this is automatically set by hardware whenever ei- ther of the two monitored analog inputs goes out of bounds. the threshold values are stored in regis- ters f8h and fah for channel 6, and in registers f9h and fbh for channel 7 respectively. the com- pare result register (crr) keeps track of the an- alog inputs exceeding the thresholds. the awd bit must be reset by the user, before re- turning from the interrupt service routine. setting this bit by software will cause a software interrupt request to be generated. 0: no analog watchdog event occurred 1: an analog watchdog event occurred bit 5 = eci : end of conversion interrupt enable. this bit masks the end of conversion interrupt re- quest. 0: mask end of conversion interrupts 1: enable end of conversion interrupts bit 4 = awdi : analog watchdog interrupt enable . this bit masks or enables the analog watchdog interrupt request. 0: mask analog watchdog interrupts 1: enable analog watchdog interrupts bit 3 = reserved. bit 2:0 = pl[2:0]: a/d interrupt priority level . these three bits allow selection of the interrupt pri- ority level for the a/d. interrupt vector register (ad_ivr) r255 - read/write register page: 63 reset value: xxxx xx10 (x2h ) bit 7:2 = v[7:2]: a/d interrupt vector. this vector should be programmed by the user to point to the first memory location in the interrupt vector table containing the starting addresses of the a/d interrupt service routines. bit 1 = w1 : word select. this bit is set and cleared by hardware, according to the a/d interrupt source. 0: interrupt source is the analog watchdog, point- ing to the lower word of the a/d interrupt service block (defined by v[7:2]). 1:interrupt source is the end of conversion inter- rupt, thus pointing to the upper word. note: when two requests occur simultaneously, the analog watchdog request has priority over the end of conversion request, which is held pending. bit 0 = reserved. forced by hardware to 0. 70 ecv awd eci awdi x pl2 pl1 pl0 70 v7 v6 v5 v4 v3 v2 w1 0 9
174/190 st90158 - electrical characteristics 10 electrical characteristics this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j =ta + pd x rthja where: t a = ambient temperature. rthja = package thermal resistance (junction-to ambient). p d =p int +p port . p int =i dd xv dd (chip internal power). p port =port power dissipation determined by the user) absolute maximum ratings note : stresses above those listed as aabsolute maximum ratingsa may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. all voltages are referenced to v ss package thermal characteristics recommended operating conditions note 1. operating temperature 0-70 c note 2. 1mhz when a/d is used symbol parameter value unit v dd supply voltage 0.3 to 7.0 v av dd a/d converter analog reference v dd -0.3 to v dd + 0.3 v av ss a/d converter v ss v ss v i input voltage 0.3 to v dd +0.3 v v ain analog input voltage (a/d converter) v ss -0.3 to v dd + 0.3 v ssa -0.3 to v dda + 0.3 v v o output voltage 0.3 to v dd +0.3 v t stg storage temperature 55 to + 150 c i inj pin injection current digital and analog input -5 to +5 ma maximum accumulated pin injection current in the device -50 to +50 ma symbol parameter package value unit rthja thermal junction to ambient tqfp80 40 c/w pqfp80 40 symbol parameter value unit min. max. t a operating temperature -40 85 c v dd operating supply voltage (rom) operating supply voltage (otp) operating supply voltage (otp low voltage version) 2.7 4.5 2.85 (1) 5.5 5.5 3.15 (1) v f intclk internal clock frequency @ 4.5v - 5.5v internal clock frequency @ 2.7v - 3.3v (rom) internal clock frequency @ 2.85v - 3.15v (otp low voltage version) 0 (2) 16 14 14 mhz
175/190 st90158 - electrical characteristics dc electrical characteristics (v dd =5v 10%, t a = -40 c+85 c, unless otherwise specified) (1) note 1: all i/o ports are configured in bidirectional weak pull-up mode with no dc load external clock pin (oscin) is driven by square wave external clock. no peripheral working. note 2: v dd =3v 10% v ilmax = 0.4 v (ttl and schmitt trigger). symbol parameter test conditio ns value unit min. typ. max. v ihck clock input high level external clock 0.7 v dd v dd + 0.3 v v ilck clock input low level external clock 0.3 0.3 v dd v v ih input high level ttl 2.0 v dd + 0.3 v cmos 0.7 v dd v dd + 0.3 v schmitt trigger 0.7 v dd v dd + 0.3 v v il input low level ttl 0.3 0.8 (2) v cmos 0.3 0.3 v dd v schmitt trigger 0.3 0.8 (2) v v ihrs reset input high level 0.7 v dd v dd + 0.3 v v ilrs reset input low level 0.3 0.3 v dd v v hyrs reset input hysteresis 0.3 1.5 v v oh output high level push pull, iload = 0.8ma v dd 0.8 v v ol output low level push pull or open drain, iload = 1.6ma 0.4 v i wpu weak pull-up current bidirectional weak pull-up, v ol = 0v 50 200 420 m a i lkio i/o pin input leakage input/tri-state, 0v < v in 176/190 st90158 - electrical characteristics ac test conditions ac electrical characteristics (v dd =5v 10%, t a = -40 c+85 c, intclk = 16 mhz unless otherwise specified) 1 note 1: all i/o ports are configured in bidirectional weak pull-up mode with no dc load, external clock pin (oscin) is driven by square wave external clock. note 2: t a =25 c. at t a 85 c the max. value is 25 m a. (v dd =3v 10%, t a =0 c+70 c, , intclk = 14 mhz unless otherwise specified) note 1: v dd =3v 5% symbol parameter intclk rom devices otp devices unit typ. max. typ. max. i ddrun run mode current, pll on 16 mhz 32 34 50 55 ma i ddwfi wfi mode current, pll on 16 mhz 11 12 16 18 ma i ddlpwfi low power wfi mode current 4 mhz/32 1.0 1.2 1.3 1.6 ma i halt halt mode current 2 310310 m a symbol parameter intclk rom devices otp lv devices (1) unit typ. max. typ. max. i ddrun run mode current, pll on 14 mhz 13 14.5 21 23.5 ma i ddwfi wfi mode current, pll on 14 mhz 5 6.5 7 8.5 ma i ddlpwfi low power wfi mode current 4 mhz/32 0.3 0.4 0.4 0.5 ma i halt halt mode current 2 5 2 5 m a 9
177/190 st90158 - electrical characteristics external bus timing table (v dd =5v 10%, t a = -40 c+85 c, cload = 50pf, intclk = 16mhz, unless otherwise specified) note: the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. the values in the right hand two columns show the timing minimum and maximum for an external clock at 24 mhz divided by 2, prescaler value of zero and zero wait status. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2*oscin period when oscin is divided by 2; oscin period / pll factor when the pll is enabled tckh = intclk high pulse width (normally = tck/2, except when intclk = oscin, in which case it is oscin high pulse width) tckl = intclk low pulse width (normally = tck/2, except when intclk = oscin, in which case it is oscin low pulse width) p = clock prescaling value (=prs; division factor = 1+p) wa = wait cycles on as; = max (p, programmed wait cycles in emr2, requested wait cycles with wait) wd = wait cycles on ds; = max (p, programmed wait cycles in wcr, requested wait cycles with wait) n symbol parameter value (note) unit formula min. max. 1 tsa (as) address set-up time before as tck*wa+tckh-9 23 ns 2 thas (a) address hold time after as tckl-4 28 ns 3 tdas (dr) as to data available (read) tck*(wd+1)+3 65 ns 4 twas as low pulse width tck*wa+tckh-5 27 ns 5 tdaz (ds) address float to ds 00ns 6 twds ds low pulse width tck*wd+tckh-5 27 ns 7 tddsr (dr) ds to data valid delay (read) tck*wd+tckh+4 35 ns 8 thdr (ds) data to ds hold time (read) 7 7 ns 9 tdds (a) ds to address active delay tckl+11 43 ns 10 tdds (as) ds to as delay tckl-4 28 ns 11 tsr/w (as) r/w set-up time before as tck*wa+tckh-17 15 ns 12 tddsr (r/w) ds to r/w and address not valid delay tckl-1 31 ns 13 tddw (dsw) write data valid to ds delay -16 -16 ns 14 tsd(dsw) write data set-up before ds tck*wd+tckh-16 16 ns 15 thds (dw) data hold time after ds (write) tckl-3 29 ns 16 tda (dr) address valid to data valid delay (read) tck*(wa+wd+1)+tckh-7 86 ns 17 tdas (ds) as to ds delay tckl-6 26 ns 1
178/190 st90158 - electrical characteristics external bus timing 9
179/190 st90158 - electrical characteristics external interrupt timing table (v dd =5v 10%, t a =-40 c +85 c, cload = 50pf, intclk = 12mhz, push-pull output configuration, un- less otherwise specified) note : the value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. the value right hand two columns show the timing minimum and maximum for an external clock at 24 mhz divided by 2, prescale value of zero and zero wait status. external interrupt timing n symbol parameter value (note) unit oscin divided by2min. oscin not divided by 2 min. min. max. 1twlr low level minimum pulse width in rising edge mode 2tpc+12 tpc+12 95 ns 2twhr high level minimum pulse width in rising edge mode 2tpc+12 tpc+12 95 ns 3twhf high level minimum pulse width in falling edge mode 2tpc+12 tpc+12 95 ns 4twlf low level minimum pulse width in falling edge mode 2tpc+12 tpc+12 95 ns 1
180/190 st90158 - electrical characteristics spi timing table (v dd =5v 10%, t a = -40 c+85 c, cload = 50pf, intclk = 12mhz, output alternate function set as push-pull) note : tpc is the oscin clock period. spi timing n symbol parameter value unit min. max. 1 tsdi input data set-up time 100 ns 2 thdi (1) input data hold time 1/2 tpc+100 ns 3 tdov sck to output data valid 100 ns 4 thdo output data hold time -20 ns 5 twskl sck low pulse width 300 ns 6 twskh sck high pulse width 300 ns 9
181/190 st90158 - electrical characteristics watchdog timing table (v dd =5v 10%, t a = -40 c+85 c, cload = 50pf, intclk = 12mhz, push-pull output configuration, unless otherwise specified ) watchdog timing n symbol parameter values unit min. max. 1 twwdol wdout low pulse width 620 ns 2 twwdoh wdout high pulse width 620 ns 3 twwdil wdin high pulse width 350 ns 4 twwdih wdin low pulse width 350 ns 1
182/190 st90158 - electrical characteristics a/d external trigger timing table a/d external trigger timing n symbol parameter oscin divided by 2 (2) oscin not divided by 2 (2) value (3) unit min. max. min. max. min. max. 1tw low external trigger pulse width 2 x tpc tpc 83 - ns 2tw high external trigger pulse distance 2 x tpc tpc 83 - ns 3tw ext external trigger active edges distance (1) 276n x tpc 138n x tpc n x 11.5 - m s 4td str extrg falling edge and first conversion start tpc 3x tpc .5 x tpc 1.5 x tpc 41.5 125 ns 9
183/190 st90158 - electrical characteristics a/d internal trigger timing table a/d internal trigger timing n symbol parameter oscin divided by 2 (2) oscin not divided by 2 (2) value (3) unit min. max. min. max. min. max. 1tw high internal trigger pulse width tpc .5 x tpc 41.5 - ns 2tw low internal trigger pulse distance 6 x tpc 3 x tpc 250 - ns 3tw ext internal trigger active edges distance (1) 276n x tpc 138n x tpc n x 11.5 - m s 4tw str internal delay between intrg rising edge and first conversion start tpc 3 x tpc .5 x tpc 1.5 x tpc 41.5 125 ns st (start conversion bit) 44 1 2 3 intrg vr0a1401 9
184/190 st90158 - electrical characteristics a/d channel enable timing table notes: 1. n = number of autoscanned channels (1 < n < 8) 2. variable clock (tpc = oscin clock period) 3. intclk = 12mhz a/d channel enable timing n symbol parameter oscin divided by 2 (2) oscin not divided by 2 (2) value (3) unit min. max. min. max. min. max. 1tw ext cen pulse width (1) 276n x tpc 138n x tpc n x 11.5 - m s 9
185/190 st90158 - electrical characteristics a/d analog specifications (vdd = 4.5v to 5.0 v) notes : 1. alsbso, as used here, has a value of avdd/256 2. including sample time 3. it must be intended as the internal series resistance before the sampling capacitor 4. this is a typical expected value, but not a tested production parameter. if v(i) is the value of the i-th transition level (0 < i < 254), the performance of the a/d converter has been valued as follows: offs et error= deviation between the actual v(0) and the ideal v(0) (=1/2 lsb) gain error= deviation between the actual v(254) and the ideal v(254) (=avcc-3/2 lsb) dnl error= max {[v(i) - v(i-1)]/lsb - 1} inl error= max {[v(i) - v(0)]/lsb - i} abs. accura cy= overall max conversion error s/n ratio has been valued by sampling a sinusoidal input waveform and then calculating its fast fourier transform. 2. absolute accuracy: 2.5 lsb at 3v. parameter typical minimum maximum units (1) notes conversion time 138 intclk (2) sample time 87.51 intclk power-up time 60 m s resolution 8 8 bits monotonicity guaranteed no missing codes guaranteed zero input reading 00 hex full scale reading ff hex offset error .5 1 lsbs (1,4) gain error .5 1 lsbs (4) diff. non linearity .3 .2 .5 lsbs (4) int. non linearity 1 lsbs (4) absolute accuracy 1 lsbs (4)(5) a vcc /a vss resistance 13.5 16 11 k w input resistance 12 8 15 k w (3) hold capacitance 30 pf input leakage 3 m a 9
186/190 st90158 - electrical characteristics multifunction timer unit external timing table notes : 1. n = 1 if the input is rising or falling edge sensitive n = 3 if the input is rising and falling edge sensitive 2. in autodiscrimination mode 3. variable clock ( tpc = oscin period ) 4. intclk = 12 mhz multifunction timer unit external timing n symbol parameter oscin divided by 2 (3) oscin not divided by 2 (3) value (4) unit note min. max. 1tw ctw external clock/trigger pulse width 2n x tpc n x tpc n x 83 - ns 1 2tw ctd external clock/trigger pulse distance 2n x tpc n x tpc n x 83 - ns 1 3tw aed distance between two active edges 6 x tpc 3 x tpc 249 - ns 4tw gw gate pulse width 12 x tpc 6 x tpc 498 - ns 5tw lba distance between tinb pulse edge and the following tina pulse edge 2xtpc tpc 83 - ns 2 6tw lab distance between tina pulse edge and the following tinb pulse edge 00-ns2 7tw ad distance between two txina pulses 0 0 - ns 2 8tw owd minimum output pulse width/distance 6 x tpc 3 x tpc 249 - ns 9
187/190 st90158 - electrical characteristics sci timing table (v dd =5v 10%, t a =-40 c to +85 c, cload = 50pf, intclk = 12mhz, output alternate function set as push-pull) note : fck = 1/tck sci timing n symbol parameter conditio n value unit min. max. f rxckin frequency of rxckin 1 x mode f ck /8 hz 16 x mode f ck /4 hz tw rxckin rxckin shortest pulse 1 x mode 4 t ck s 16 x mode 2 t ck s f txckin frequency of txckin 1 x mode f ck /8 hz 16 x mode f ck /4 hz tw txckin txckin shortest pulse 1 x mode 4 t ck s 16 x mode 2 t ck s 1ts ds ds (data stable) before rising edge of rxckin 1 x mode reception with rxckin t pc /2 ns 2td d1 txckin to data out delay time 1 x mode transmission with external clock c load <100pf 2.5 t pc ns 3td d2 clkout to data out delay time 1 x mode transmission with clkout 350 ns 1
188/190 st90158 - general information 11 general information 11.1 package mechanical data figure 89. 80-pin thin plastic quad flat package 11.2 80-pin plastic quad flat package tqfp80 dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.009 0.013 0.015 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.65 0.026 k 0 3.5 0.75 0 3.5 0.75 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n80 nd20ne20 0.10mm .004 seating plane pqfp080 dim mm inches min typ max min typ max a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 22.95 23.20 23.45 0.904 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.40 0.724 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 0.80 0.031 k 0 7 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 number of pins n80 nd24ne16 0.10mm .004 seating plane 1
189/190 st90158 - general information 80-pin ceramic quad flat package 11.3 ordering information dim mm inches min typ max min typ max a 3.24 0.128 a1 0.20 0.008 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.13 0.15 0.23 0.005 0.006 0.009 d 23.35 23.90 24.45 0.919 0.941 0.963 d1 19.57 20.00 20.43 0.770 0.787 0.804 d3 18.40 0.724 e 17.35 17.90 18.45 0.683 0.705 0.726 e1 13.61 14.00 14.39 0.536 0.551 0.567 e3 12.00 0.472 e 0.80 0.031 g 13.75 14.00 14.25 0.541 0.551 0.561 g1 19.75 20.00 20.25 0.778 0.787 0.797 g2 1.06 0.042 l 0.35 0.80 0.014 0.031 number of pins n80 cqfp080 part number program memory (bytes) ram (bytes) temp. range operating supply package st90135m4q6 16k rom 512 -40 c +85 c 5v @ 16mhz 3v @ 14 mhz pqfp80 st90135m5q6 24k rom 768 st90135m6q6 32k rom 1k st90158m7q6 48k rom 1.5k st90158m9q6 64k rom 2k st90158m9t1 0 c +70 c 3v @ 14 mhz tqfp80 st90e158m9g0 64k eprom 2k + 25 c 5v @ 16mhz cqfp80-w st90e158m9lvg0 3v @ 14 mhz cqfp80-w st90t158m9q6 64k otp 2k -40 c +85 c 5v @ 16mhz pqfp80 st90t158m9lvq1 0 c +70 c 3v @ 14 mhz pqfp80 st90t158m9lvt1 tqfp80 st90r158q6 romless 2k -40 c +85 c 5v @ 16mhz pqfp80 st90r158t1 romless 2k 0 c +70 c 3v @ 14mhz tqfp80 9
190/190 st90158 - general information notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain sweden - switzerland - united kingdom - u.s.a. http:// www.st.com 1

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